Implement 1x4 de-multiplexer using data flow modeling in verilog, also write its test bench.

Expert Solution

verilog code using Data flow modelling:

module demux(in,s,out1,out2,out3,out4);
input in;
input [1:0]s;
output out1,out2,out3,out4;

assign out1=in&(~s[1])&(~s[0]);
assign out2=in&(~s[1])&(s[0]);
assign out3=in&(s[1])&(~s[0]);
assign out4=in&(s[1])&(s[0]);

endmodule

Test Bench:

module tb_demux;
reg in;
reg [1:0]sel;
wire out1,out2,out3,out4;

demux d1(in,sel,out1,out2,out3,out4);

initial

$monitor ($time,"in=%b,sel=%b,out1=%b,out2=%b,out3=%b,out4=%b",in,sel,out1,out2,out3,out4);

initial

   begin
in=1'b1;
   #10   sel=2'b00;
   #10   sel=2'b01;
   #10    sel=2'b10;
   #10    sel=2'b11;
   #10    in=1'b0;
   #10    $finish;
   end

endmodule

Manojponduru answered 10 months ago

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