Implement 1x4 de-multiplexer using data flow modeling in verilog, also write its test bench.

Expert Solution

verilog code using Data flow modelling:

module demux(in,s,out1,out2,out3,out4);
input in;
input [1:0]s;
output out1,out2,out3,out4;

assign out1=in&(~s[1])&(~s[0]);
assign out2=in&(~s[1])&(s[0]);
assign out3=in&(s[1])&(~s[0]);
assign out4=in&(s[1])&(s[0]);

endmodule

Test Bench:

module tb_demux;
reg in;
reg [1:0]sel;
wire out1,out2,out3,out4;

demux d1(in,sel,out1,out2,out3,out4);

initial

$monitor ($time,"in=%b,sel=%b,out1=%b,out2=%b,out3=%b,out4=%b",in,sel,out1,out2,out3,out4);

initial

   begin
in=1'b1;
   #10   sel=2'b00;
   #10   sel=2'b01;
   #10    sel=2'b10;
   #10    sel=2'b11;
   #10    in=1'b0;
   #10    $finish;
   end

endmodule

Manojponduru answered 4 months ago

Implement a JK Flip flop using behavioral modeling in verilog, also write its test bench code.

Implement a 4x4 multiplier using gate level (verilog code and test bench)

Type up Verilog Verilog program , test bench and screenshot of the wavefore using verilog xilinx....

Type up Verilog Verilog program , test bench and screenshot of the wavefore using verilog xilinx. (PLEASE ONLY ANSWER IF YOU UNDERSTAND HOW TO USE XILINX. ******************no need to show me the state diagram or state table just the verilog code , test bench and the screenshot of the waveforem **************** Implement the function given below using each of the following methods. As few 16-1 multiplexers as possible. Behavioral Verilog. F( w , x, y , z) = ?(2 ,...

Using the conditional assignment statements, write the verilog code for 16:1 Mux. Write the test bench...

Using the conditional assignment statements, write the verilog code for 16:1 Mux. Write the test bench for this module.

Write the VERILOG code for an arithmetic/logic unit (ALU) with a test bench that does the...

Write the VERILOG code for an arithmetic/logic unit (ALU) with a test bench that does the following with 4 bit inputs , and can be tested in on nexys 4 board This is to be implement on : ISE Design Suite - Xilinx /* ALU Arithmetic and Logic Operations ---------------------------------------------------------------------- |ALU_Sel| ALU Operation ---------------------------------------------------------------------- | 0000 | ALU_Out = A + B; ---------------------------------------------------------------------- | 0001 | ALU_Out = A - B; ---------------------------------------------------------------------- | 0010 | ALU_Out = A * B;...

Can anyone write a Verilog code and a test bench for a universal shift register with...

Can anyone write a Verilog code and a test bench for a universal shift register with 4 bits using D flip flop? Thanks

Write the Verilog code and test bench for the following circuits: - Mealy State machine design...

Write the Verilog code and test bench for the following circuits: - Mealy State machine design for a Serial Adder Circuit - Moore State Machine design for a Serial Adder Circuit

code an 8 bit LFSR random number generator in system verilog. Write a test bench, load...

code an 8 bit LFSR random number generator in system verilog. Write a test bench, load the seed 11111111, and generate the first 10 random numbers.

The goal in this experiment is to implement a 0-12 counter with a test bench that...

The goal in this experiment is to implement a 0-12 counter with a test bench that displays the output of each of the flip-flops in the counter. A behavioral code should be written for this experiment. Set the time format to 1 nanosecond with a precision of 100 picosecond.

verilog code of a 64 x64 array with 128 parameters please include test bench

Question