Question

In: Electrical Engineering

Using the conditional assignment statements, write the verilog code for 16:1 Mux. Write the test bench...

Using the conditional assignment statements, write the verilog code for 16:1 Mux. Write the test bench for this module.

Expert Solution

//Code

module mux_16_1(

input [15:0] din,

input [3:0] sel,

output reg dout

);

always @ (sel or din)

dout = (sel == 4'b0000)? din[0] :

((sel == 4'b0001)? din[1] :

((sel == 4'b0010)? din[2] :

((sel == 4'b0011)? din[3] :

((sel == 4'b0100)? din[4] :

((sel == 4'b0101)? din[5] :

((sel == 4'b0110)? din[6] :

((sel == 4'b0111)? din[7] :

((sel == 4'b1000)? din[8] :

((sel == 4'b1001)? din[9] :

((sel == 4'b1010)? din[10] :

((sel == 4'b1011)? din[11] :

((sel == 4'b1100)? din[12] :

((sel == 4'b1101)? din[13] :

((sel == 4'b1110)? din[14] :

((sel == 4'b1111)? din[15] :

1'bz)))))))))))))));

endmodule

///testbench

module tb_mux_16_1;

// Inputs

reg [15:0] din;

reg [3:0] sel;

// Outputs

wire dout;

// Instantiate the Unit Under Test (UUT)

mux_16_1 uut (

.din(din),

.sel(sel),

.dout(dout)

);

initial begin

// Initialize Inputs

din = 0;

sel = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

din = 16'b1010101010101010;

#20 sel = 4'b0000;

#20 sel = 4'b0001;

#20 sel = 4'b0010;

#20 sel = 4'b0011;

#20 sel = 4'b0100;

#20 sel = 4'b0101;

#20 sel = 4'b0110;

#20 sel = 4'b0111;

#20 sel = 4'b1000;

#20 sel = 4'b1001;

#20 sel = 4'b1010;

#20 sel = 4'b1011;

#20 sel = 4'b1100;

#20 sel = 4'b1101;

#20 sel = 4'b1110;

#20 sel = 4'b1111;

end

endmodule

//Simulated waveform

Manojponduru answered 2 years ago

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Using the conditional assignment statements, write the verilog code for 16:1 Mux. Write the test bench...

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