Write the VERILOG code for an arithmetic/logic unit (ALU) with a test bench that does the...

Write the VERILOG code for an arithmetic/logic unit (ALU) with a test bench that does the following with 4 bit inputs , and can be tested in on nexys 4 board

This is to be implement on : ISE Design Suite - Xilinx

/* ALU Arithmetic and Logic Operations
----------------------------------------------------------------------
|ALU_Sel|   ALU Operation
----------------------------------------------------------------------
| 0000  |   ALU_Out = A + B;
----------------------------------------------------------------------
| 0001  |   ALU_Out = A - B;
----------------------------------------------------------------------
| 0010  |   ALU_Out = A * B;
----------------------------------------------------------------------
| 0011  |   ALU_Out = A / B;
----------------------------------------------------------------------
| 0100  |   ALU_Out = A << 1;
----------------------------------------------------------------------
| 0101  |   ALU_Out = A >> 1;
----------------------------------------------------------------------
| 0110  |   ALU_Out = A rotated left by 1;
----------------------------------------------------------------------
| 0111  |   ALU_Out = A rotated right by 1;
----------------------------------------------------------------------
| 1000  |   ALU_Out = A and B;
----------------------------------------------------------------------
| 1001  |   ALU_Out = A or B;
----------------------------------------------------------------------
| 1010  |   ALU_Out = A xor B;
----------------------------------------------------------------------
| 1011  |   ALU_Out = A nor B;
----------------------------------------------------------------------
| 1100  |   ALU_Out = A nand B;
----------------------------------------------------------------------
| 1101  |   ALU_Out = A xnor B;
----------------------------------------------------------------------
| 1110  |   ALU_Out = 1 if A>B else 0;
----------------------------------------------------------------------
| 1111  |   ALU_Out = 1 if A=B else 0;

Expert Solution

Manojponduru answered 1 year ago

write an Arithmetic Logic Unit (ALU) in verilog.

Write the VERILOG code for an arithmetic/logic unit (ALU) following , and can be tested in...

Write the VERILOG code for an arithmetic/logic unit (ALU) following , and can be tested in on nexys 4 board This is to be implement on : ISE Design Suite - Xilinx /* ALU Arithmetic and Logic Operations ---------------------------------------------------------------------- |ALU_Sel| ALU Operation ---------------------------------------------------------------------- | 0000 | ALU_Out = A + B; ---------------------------------------------------------------------- | 0001 | ALU_Out = A - B; ---------------------------------------------------------------------- | 0010 | ALU_Out = A * B; ---------------------------------------------------------------------- | 0011 | ALU_Out = A / B; ---------------------------------------------------------------------- |...

The heart of a computer system is an ARITHMETIC AND LOGIC UNIT (ALU) which is responsible...

The heart of a computer system is an ARITHMETIC AND LOGIC UNIT (ALU) which is responsible for executing arithmetic (e.g., addition, subtraction, etc.) and logic (e.g., AND, OR, etc.) operations. In this project, you will design, simulate, and implement a simple 1-bit ALU. The truth table for ALU is given below: Operation Selection Inputs Operation Output(s) S0 S1 A B 0 0 A AND B AB 0 1 A NOR B (A+B)’ 1 0 A XNOR B (A⊕B)’ 1 1...

Can anyone write a Verilog code and a test bench for a universal shift register with...

Can anyone write a Verilog code and a test bench for a universal shift register with 4 bits using D flip flop? Thanks

draw state machine and write verilog code of an ALU unit that shifts left when the...

draw state machine and write verilog code of an ALU unit that shifts left when the control signal 'OP' is 00, shifts right when control is ''01'' and increments when control is ''10''. Fpr control ''11'' , it does nothing. inputs are Date [3:0] and clk, and the output is Out [3:0]

Write the Verilog code and test bench for the following circuits: - Mealy State machine design...

Write the Verilog code and test bench for the following circuits: - Mealy State machine design for a Serial Adder Circuit - Moore State Machine design for a Serial Adder Circuit

Using the conditional assignment statements, write the verilog code for 16:1 Mux. Write the test bench...

Using the conditional assignment statements, write the verilog code for 16:1 Mux. Write the test bench for this module.

code an 8 bit LFSR random number generator in system verilog. Write a test bench, load...

code an 8 bit LFSR random number generator in system verilog. Write a test bench, load the seed 11111111, and generate the first 10 random numbers.

1. Write Verilog code and test bench for Moore FSM having a single input line ‘X’...

1. Write Verilog code and test bench for Moore FSM having a single input line ‘X’ and a single output-line ’Z’. An output of 1 is to be produced coincident with the pattern 1101 and an output of ‘ 0’ is to be produced for all the other sequences and simulate it.

Implement a 4x4 multiplier using gate level (verilog code and test bench)

Question