Question

Write the Verilog code and test bench for the following circuits:

- Mealy State machine design for a Serial Adder Circuit

- Moore State Machine design for a Serial Adder Circuit

Answer 1

Mealy state machine design for serial adder:

State diagram for serial adder

module SA(

    input A,

    input B,

    output F,

    output Cout,

    input clk,

    input rst

    );

// Define State Codes

localparam S0 = 2'b00;

localparam S1 = 2'b01;

localparam S2 = 2'b10;

localparam S3 = 2'b11;

reg [1:0] pState, nState;

// Combinational Logic: Next State Logic

always @ (pState, A, B)

begin

    case (pState)

        S0:begin

            if (A == 1'b0 && B == 1'b0)

                nState = S0;

            else if (A == 1'b1 && B == 1'b1)

                nState = S2;

            else

                nState = S1;

            end

        S1:

            if (A == 1'b0 && B == 1'b0)

                nState = S0;

            else if (A == 1'b1 && B == 1'b1)

                nState = S2;

            else

                nState = S1;

        S2:

            if (A == 1'b0 && B == 1'b0)

                nState = S1;

            else if (A == 1'b1 && B == 1'b1)

                nState = S3;

            else

                nState = S2;

        S3:

            if (A == 1'b0 && B == 1'b0)

                nState = S1 ;

            else if (A == 1'b1 && B == 1'b1)

                nState = S3;

            else

                nState = S2;

        default:

            nState = S0;

    endcase

end

// State Registers

always @ (posedge(clk), posedge(rst))

begin

    if (rst == 1'b1)

        pState <= S0;

    else

        pState <= nState;

end

// Output Logic

assign F = (pState == S1 || pState == S3) ? 1'b1 : 1'b0;

assign Cout = (pState == S2 || pState == S3) ? 1'b1 : 1'b0;

endmodule

2. Verilog code for Moore type srials adder:

module sadd (a, b, s, clock, clear);
> parameter s0 = 1'b0, s1 = 1'b1;
> input a, b, clock, clear;
> output s;
> reg s;
> reg ps, ns;
>
> always @(posedge clock or posedge clear) begin
> if (clear) begin
> ps = s0;
> end
> else begin
> ps = ns;
> end
> end
>
> always @(ps or a or b) begin
> case (ps)
> s0: begin
> case ({a,b})
> 2'b00: begin
> ns = s0;
> s = 1;
> end
> 2'b01: begin
> ns = s1;
> s = 0;
> end
> 2'b10: begin
> ns = s1;
> s = 0;
> end
> 2'b11: begin
> ns = s1;
> s = 1;
> end
> s = 0;
> end
> 2'b01: begin
> ns = s0;
> s = 1;
> end
> 2'b10: begin
> ns = s0;
> s = 1;
> end
> 2'b11: begin
> ns = s1;
> s = 0;
>
> end
> default: begin
> ns = s0;
> s = 0;
> end
> endcase
> end
> s1: begin
> case ({a,b})
> 2'b00: begin
> ns = s0;
> default: begin
> ns = s0;
> s = 0;
> end
> endcase
> end
> default: begin
> ns = s0;
> end
> endcase
> end
>
> endmodule