Implement a 4x4 multiplier using gate level (verilog code and test bench)

Expert Solution

//verlog code

`timescale 1ns / 1ps

module mul44(c, a, b);

output [8:0] c;
input [3:0] a;
input [3:0] b;

assign c = a * b;

endmodule
-------------------------------

------------------------------------

//verilog test bench

`timescale 1ns / 1ps

module mult44_tb;

   // Inputs
   reg [3:0] a;
   reg [3:0] b;

// Outputs
wire [8:0] c;

   // Instantiate the Unit Under Test (UUT)
   mul44 uut (
       .c(c),
       .a(a),
       .b(b)
   );

   initial begin

       #100;


a=4'b1000;
       b=4'b1100;
       #100;
   end

endmodule

--------------------------

Manojponduru answered 1 year ago

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Implement a 4x4 multiplier using gate level (verilog code and test bench)

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