Question

code an 8 bit LFSR random number generator in system verilog. Write a test bench, load the seed 11111111, and generate the first 10 random numbers.

Answer 1

module lfsrcode (output reg [7:0]out, input clk, input rst);

wire fdbk;

assign fdbk = ~(out[7] ^ out[6]);

always @(posedge clk, negedge rst)

begin

if (!rst)

out = 8'b11111111;

else

out = {out[6:0],fdbk};

end

endmodule

//testbench//

`timescale 1ns/1ps

module lfsrcode_test();

    reg clk,rst;

    wire [7:0]out;

    Lfsrcode UUT(.out(out),.clk(clk),.rst(rst));

    initial

        begin

        $display(“time,\t out,”);

        $monitor(“%g,\t %b”,$time,out);
#500 $stop;

        end

        always

            begin

            #50 clk_tb=1?b1;

            #50 clk_tb=1?b0;

            end

endmodule