Question

1. Write Verilog code and test bench for Moore FSM having a single input line ‘X’ and a single output-line ’Z’. An output of 1 is to be produced coincident with the pattern 1101 and an output of ‘ 0’ is to be produced for all the other sequences and simulate it.

Answer 1

The verilog code:

module moore_fsm_1101_seq(reset,clk,X,Z);
input reset,X,clk; //inputs to the state machine
output reg Z; //output
reg [2:0] present_state,next_state; //resent and next state of state machine
parameter s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101; //encoding each state with 001,010,011,100,101
initial
begin //out=1 when success else out=0 in error
present_state=0;
next_state=0;
end
always@(posedge clk)
begin
if(reset==1)
present_state<=s1;
else
present_state<=next_state;
end
always@(present_state or X)
begin
case(present_state)
s1:begin
if(X==1)
next_state<=s2;
else
next_state<=s1;
Z=1'b0;
end
s2:begin
if(X==1)
next_state<=s3;
else
next_state<=s1;
Z=1'b0;
end
s3:begin if(X==1)
next_state<=s3;
else
next_state<=s4;
Z=1'b0;
end
s4:begin if(X==1)
next_state<=s5;
else
next_state<=s1;
Z=1'b0;
end
s5:begin if(X==1)
next_state<=s3;
else
next_state<=s1;
Z=1'b1;
end
endcase
end
endmodule

Code snippet:

Test bench code:

module moore_fsm_tb;
reg reset,X,clk; //INPUTS are declared as reg
wire Z; //outputs are declared as wire
//module instantiation
moore_fsm_1101_seq m1(reset,clk,X,Z);
initial
//input assigning
begin
reset=1;clk=0;X=0;
#10 reset=0;
#10 X=0;
#10 X=1;
#10 X=1;
#10 X=0;
#10 X=1;
#10 X=1;
#10 X=0;
#10 X=1;
#10 X=0;
#10 X=0;
#10 X=1;
#10 X=1;
#10 X=1;
#10 X=0;
#10 X=1;
#10 X=0;
#10 X=1;
#10 X=1;
end
always
#5 clk=~clk; //clock declaration
initial
#200 $finish ;
endmodule

code snippet:

Simulation Results:

Please see the code snippet for the indentation.

I write the code in vivado tool. The code is with overlap sequence i have written here,

Please upvote this.