Question

Analyze the following Verilog code and write down its output as pictured in the code.

module blocking;

reg [0:7] A, B;

initial begin: init1

A = last decimal digit of your ID;

#1 A = A + 1; // blocking procedural assignment

B = A + 1;

$display("Output 1: A= %b B= %b", A, B );

A = last decimal digit of your ID;

#1 A <= A + 1;

B <= A + 1;

#1 $display ("Output 2: A= %b B= %b", A, B );

end

endmodule

Answer 1

Analyzing the code:

Here blocking procedural assignment (=) and non blocking procedural assignment (<=) statements are used.

Given A and B are 8 bit numbers. Initially Let A=7(last digit of id number).

In first case Using blocking procedural assignment:

#1 A=A+1 means after 1 time unit output will be A= 7+1=8,

B=A+1 = 8+1 = 9 .

While using blocking procedural assignment ,the value of A gets updated and it will be used in next statements.

In second case Using non blocking procedural assignment:

#1A<=A+1 means after one time unit the value of will be A= 7+1=8

B<=A+1=7+1=8

In case of nonblocking procedural assignment the old value (initial value) of A will be used in all statements.

The purpose of Non blocking procedural assignment is to use the previous values to the variables at the start of current time unit and assigning new values to variables at the end of current time unit.

Blocking procedural assignment are used for combinational circuits and nonblocking for sequential circuits.

Here let last digit of id number be 7

OUTPUT:

Output1:A=00001000 B=00001001

Output2:A=00001000 B=00001000