In: Electrical Engineering
SOLVE FOLLOWING
a. Desgin and VERILOG code of a 3 bit up down counter USING T FLIP FLOP.....
b. using behavioural module.Write a verilog discription of an N-BIT up down binary counter. Record the simulation output waveform in observation.....
// PART A) 3 bit Counter UP DOWN using TFF
module tff (
input clk, // Clock
input rst, // Reset
input T, // T input
output Q // Output
);
reg temp;
always @ (posedge clk)
begin
if (rst) // synchronous and active high reset
temp <= 1'b0;
else
begin
if (T)
temp <= ~temp; // toggle output
else
temp <= temp; // maintains previous state
end
end
assign Q = temp;
endmodule
module counter_top ( // UP DOWN counter using TFF
input clk,
input rst,
input updown, // updown = 0 counter increments ; updown
= 1 counter decrements
output [2:0] count
);
wire temp2, temp1, temp0, Q2, Q1, Q0;
assign temp2 = (~Q1 & ~Q0 & updown) | (Q1 & Q0 &
~updown);
assign temp1 = (~Q0 & updown) | (Q0 & ~updown);
assign temp0 = 1'b1;
tff m2 (.clk(clk), .rst(rst), .T(temp2), .Q(Q2));
tff m1 (.clk(clk), .rst(rst), .T(temp1), .Q(Q1));
tff m0 (.clk(clk), .rst(rst), .T(temp0), .Q(Q0));
assign count = {Q2, Q1, Q0};
endmodule
module counter_tb;
reg clk , rst, updown;
wire [2:0] count;
counter_top COUNTER_TFF (.clk(clk), .rst(rst), .updown(updown),
.count(count));
always
#5 clk = ~clk;
initial
begin
clk = 1'b0;
rst = 1'b1;
repeat(2)
@(negedge clk);
rst = 1'b0;
updown = 1'b0;
repeat(10)
@(negedge clk);
updown = 1'b1;
repeat(5)
@(negedge clk);
updown = 1'b0;
repeat(4)
@(negedge clk);
$finish;
end
initial
begin
$recordfile("file1.trn");
$recordvars();
end
endmodule
// PART B) N bit UP DOWN COUNTER verilog behavioral code
module counter_updown #(parameter WIDTH = 4) (
input clk,
input rst,
input updown,
output reg [WIDTH-1:0] count
);
always @ (posedge clk)
begin
if (rst) // Synchronous active high reset
count <= {WIDTH{1'b0}};
else
begin
if (!updown) // Count up
count <= count + 1'b1;
else // Count down
count <= count - 1'b1;
end
end
endmodule
module counter_tb;
reg clk , rst, updown;
wire [2:0] count;
counter_updown #(.WIDTH(3)) COUNTER_BEHAVE (.clk(clk), .rst(rst),
.updown(updown), .count(count));
always
#5 clk = ~clk;
initial
begin
clk = 1'b0;
rst = 1'b1;
repeat(2)
@(negedge clk);
rst = 1'b0;
updown = 1'b0;
repeat(10)
@(negedge clk);
updown = 1'b1;
repeat(5)
@(negedge clk);
updown = 1'b0;
repeat(4)
@(negedge clk);
$finish;
end
initial
begin
$recordfile("file1.trn");
$recordvars();
end
endmodule