Question

Write the Verilog Code for the module to multiply two 7-bit numbers using the array multiplie

Answer 1

Here i designed the 7bit array multipliere by using 1 bit multiplier,fulladder,halfadder module instantiations.

Fulladdercode:

module fulladder(a,b,cin,s,cy);
input a,b,cin;
output wire s,cy;
assign s=a^b^cin;
assign cy=((a^b)&cin)| (a&b);
endmodule

Halfadder code:

module halfadder(a,b,s,cy);
input a,b;
output wire s,cy;
assign s=a^b;
assign cy=a&b;
endmodule

1 bit multiplier:

module multiplier_1bit(a,b,p);
input a,b; //1 bit inputs
output wire p; //1 bit output
assign p=a&b; //product assignment
endmodule

The verilog code for the given problem: 7bit array multiplier:

module array_multiplier_7bit(a,b,prod);
input [6:0] a,b;
output wire [13:0] prod;
wire [6:0]p0,p1,p2,p3,p4,p5,p6; //which stores the 1 bit multiplier outputs
wire [41:0] cy; //stores the carry value while adding 1 bit products
wire [40:0]s;
//The below 1 bit module instantiation stores p0=B*A0
multiplier_1bit m1(a[0],b[0],p0[0]);
multiplier_1bit m2(a[0],b[1],p0[1]);
multiplier_1bit m3(a[0],b[2],p0[2]);
multiplier_1bit m4(a[0],b[3],p0[3]);
multiplier_1bit m5(a[0],b[4],p0[4]);
multiplier_1bit m6(a[0],b[5],p0[5]);
multiplier_1bit m7(a[0],b[6],p0[6]);
//The below 1 bit module instantiation stores p1=B*A1
multiplier_1bit mm1(a[1],b[0],p1[0]);
multiplier_1bit mm2(a[1],b[1],p1[1]);
multiplier_1bit mm3(a[1],b[2],p1[2]);
multiplier_1bit mm4(a[1],b[3],p1[3]);
multiplier_1bit mm5(a[1],b[4],p1[4]);
multiplier_1bit mm6(a[1],b[5],p1[5]);
multiplier_1bit mm7(a[1],b[6],p1[6]);
//The below 1 bit module instantiation stores p2=B*A2
multiplier_1bit mmm1(a[2],b[0],p2[0]);
multiplier_1bit mmm2(a[2],b[1],p2[1]);
multiplier_1bit mmm3(a[2],b[2],p2[2]);
multiplier_1bit mmm4(a[2],b[3],p2[3]);
multiplier_1bit mmm5(a[2],b[4],p2[4]);
multiplier_1bit mmm6(a[2],b[5],p2[5]);
multiplier_1bit mmm7(a[2],b[6],p2[6]);
//The below 1 bit module instantiation stores p3=B*A3
multiplier_1bit mmm11(a[3],b[0],p3[0]);
multiplier_1bit mmm22(a[3],b[1],p3[1]);
multiplier_1bit mmm33(a[3],b[2],p3[2]);
multiplier_1bit mmm44(a[3],b[3],p3[3]);
multiplier_1bit mmm55(a[3],b[4],p3[4]);
multiplier_1bit mmm66(a[3],b[5],p3[5]);
multiplier_1bit mmm77(a[3],b[6],p3[6]);
//The below 1 bit module instantiation stores p4=B*A4
multiplier_1bit mm11(a[4],b[0],p4[0]);
multiplier_1bit mm22(a[4],b[1],p4[1]);
multiplier_1bit mm33(a[4],b[2],p4[2]);
multiplier_1bit mm44(a[4],b[3],p4[3]);
multiplier_1bit mm55(a[4],b[4],p4[4]);
multiplier_1bit mm66(a[4],b[5],p4[5]);
multiplier_1bit mm77(a[4],b[6],p4[6]);
//The below 1 bit module instantiation stores p5=B*A5
multiplier_1bit m11(a[5],b[0],p5[0]);
multiplier_1bit m22(a[5],b[1],p5[1]);
multiplier_1bit m33(a[5],b[2],p5[2]);
multiplier_1bit m44(a[5],b[3],p5[3]);
multiplier_1bit m55(a[5],b[4],p5[4]);
multiplier_1bit m66(a[5],b[5],p5[5]);
multiplier_1bit m77(a[5],b[6],p5[6]);
//The below 1 bit module instantiation stores p6=B*A6
multiplier_1bit mn11(a[6],b[0],p6[0]);
multiplier_1bit mn22(a[6],b[1],p6[1]);
multiplier_1bit mn33(a[6],b[2],p6[2]);
multiplier_1bit mn44(a[6],b[3],p6[3]);
multiplier_1bit mn55(a[6],b[4],p6[4]);
multiplier_1bit mn66(a[6],b[5],p6[5]);
multiplier_1bit mn77(a[6],b[6],p6[6]);
//full adder and half adder block instantiations for calculating the product.
halfadder h1(p0[1],p1[0],s[0],cy[0]); //prod[1]

fulladder f1(p0[2],p1[1],cy[0],s[1],cy[1]);
halfadder h11(s[1],p2[0],s[2],cy[2]); //prod[2]

fulladder f2(p0[3],p1[2],cy[1],s[3],cy[3]);
fulladder f3(s[3],cy[2],p2[1],s[4],cy[4]);
halfadder h12(s[3],p3[0],s[5],cy[5]); //prod[3]

fulladder f4(p0[4],p1[3],cy[3],s[5],cy[6]);
fulladder f5(s[5],cy[4],p2[2],s[6],cy[7]);
fulladder f6(s[6],cy[5],p3[1],s[7],cy[8]);
halfadder h31(s[7],p4[0],s[8],cy[9]); //prod[4]

fulladder f7(p0[5],p1[4],cy[6],s[9],cy[10]);
fulladder f8(s[9],cy[7],p2[3],s[10],cy[11]);
fulladder f9(s[10],cy[8],p3[2],s[11],cy[12]);
fulladder f10(s[11],cy[9],p4[1],s[12],cy[13]);
halfadder h32(s[12],p5[0],s[13],cy[14]); //prod[5]

fulladder f11(p0[6],p1[5],cy[10],s[14],cy[15]);
fulladder f12(s[14],cy[11],p2[4],s[15],cy[16]);
fulladder f13(s[15],cy[12],p3[3],s[16],cy[17]);
fulladder f14(s[16],cy[13],p4[2],s[17],cy[18]);
fulladder f15(s[17],cy[14],p5[1],s[18],cy[19]);
halfadder h41(s[18],p6[0],s[19],cy[20]); //prod[6]

halfadder h51(p1[6],cy[15],s[20],cy[21]);
fulladder f16(s[20],p2[5],cy[16],s[21],cy[22]);
fulladder f17(s[21],p3[4],cy[17],s[22],cy[23]);
fulladder f18(s[22],p4[3],cy[18],s[23],cy[24]);
fulladder f19(s[23],p5[2],cy[19],s[24],cy[25]);
fulladder f20(s[24],p6[1],cy[20],s[25],cy[26]); //prod[7]

fulladder f21(p2[6],p3[5],cy[21],s[26],cy[27]);
fulladder f22(s[26],cy[22],p4[4],s[27],cy[28]);
fulladder f23(s[27],cy[23],p5[3],s[28],cy[29]);
fulladder f24(s[28],cy[24],p6[2],s[29],cy[30]);
fulladder f25(s[29],cy[25],cy[26],s[30],cy[31]); //prod[8]

fulladder f26(p3[6],p4[5],cy[27],s[31],cy[32]);
fulladder f27(s[31],cy[28],p5[4],s[32],cy[33]);
fulladder f28(s[32],cy[29],p6[3],s[33],cy[34]);
fulladder f29(s[33],cy[30],cy[31],s[34],cy[35]); //prod[9]

fulladder f30(p4[6],p5[5],cy[32],s[35],cy[36]);
fulladder f31(s[35],cy[33],p6[4],s[36],cy[37]);
fulladder f32(s[36],cy[34],cy[35],s[37],cy[38]); //prod[10]

fulladder f33(p5[6],p6[5],cy[36],s[38],cy[39]);
fulladder f34(s[38],cy[37],cy[38],s[39],cy[40]); //prod[11]

fulladder f35(p6[6],cy[34],cy[35],s[40],cy[41]); //prod[12] =s[40] ,prod[13]=cy[41]

assign prod[0]=a[0]&b[0];
assign prod[1]=s[0];
assign prod[2]=s[2];
assign prod[3]=s[5];
assign prod[4]=s[8];
assign prod[5]=s[13];
assign prod[6]=s[19];
assign prod[7]=s[25];
assign prod[8]=s[30];
assign prod[9]=s[34];
assign prod[10]=s[37];
assign prod[11]=s[39];
assign prod[12]=s[40];
assign prod[13]=cy[41];
endmodule

Code snippets:

Simulation Results for some inputs:

Here i take few inputs for the output.I changed the radix of a,b,prod to unsigned decimal in simulaiton results for better understanding.

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