Question

Write a Verilog code to implement 16 bit LFSR

Answer 1

Your specs are not clear for linear feedback shift register but you can modify the code provided below as per your need.

Working verilog code to implement 16 bit LFSR:

module lfsr

(input clk,clr,

output y);

//clk->clock, clr->posedge clear,y=pne bit serial output

reg [15:0]q;

//q->16 bit intermediate line for shift register

//q0 is assigned to y ;right shift

assign y=q[0];

wire w1,w2,w3;

//w1,w2,w3 has xor operation between mentioned bits

assign w1=q[13]^q[15],

w2=w1^q[12],

w3=w2^q[10];

always@(posedge clk,posedge clr)

begin

//if clr=1, load the initial bits

if(clr)

q<=16'b1010110011100001;

//else right shift and load w3 as msb bit

else

q<={w3,q[15:1]};

end

endmodule

Code Screenshots: