Please Create the Verilog/Vivado Code For:
An LFSR Pseudonumber generator, and the testbench for test
it,
please comment and explain the answer as much as
possible
if possible, post Pic of the waveform
simulation!
(Write/Design) both the RTL and Testbench using the Verilog HDL
language of the five input majority using the structure modeling
approach.
NOTE: Design means RTL code and Testbench covering all possible
corner cases
Verilog counter problem:
Using the attached 4-bit up-counter module and testbench as a
template, write a Verilog module that implements a certain 4-bit
counter. The module should include two more input variables:
“updown” and “count2”.
If “updown” is 1, the circuit should count up (by 1s); if it is
0 it should count down (by 1s).
If “count2” has a value of 1, the circuit should instead count
up by 2s; otherwise it will have no effect (the circuit counts...
Verilog counter problem:
Using the attached 4-bit up-counter module and testbench as a
template, write a Verilog module that implements a certain 4-bit
counter. The module should include two more input variables:
“updown” and “count2”.
If “updown” is 1, the circuit should count up (by 1s); if it is
0 it should count down (by 1s).
If “count2” has a value of 1, the circuit should instead count
up by 2s; otherwise it will have no effect (the circuit counts...