Question

Write Verilog code for a Moore detector that detects sequences 10111 and 10101 on its j input and creates a pulse of exactly one clock duration on its output. The output becomes 1 if either of the sequences, or an overlap of the two is detected. A) Show the state diagram of this machine. B) Write complete Verilog for the design. C) Write a testbench and test your state machine using ModelSim.

Answer 1

B.

module moore_detector ( input clk, data_in, reset,
output reg detected
);

reg [2:0] state;
parameter S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6;

always @ (posedge clk or reset) begin
if (reset)
state <= S0;
else
case (state)
S0: if (data_in) state <= S1; else state <= S0;
S1: if (data_in) state <= S1; else state <= S2;
S2: if (data_in) state <= S3; else state <= S0;
S3: if (data_in) state <= S4; else state <= S5;
S4: if (data_in) state <= S6; else state <= S2;
S5: if (data_in) state <= S6; else state <= S0;
S6: if (data_in) state <= S1; else state <= S2;
default: state <= S0;
endcase
end
  
always @ (state) begin
case (state)
S0: detected = 1'b0;
S1: detected = 1'b0;
S2: detected = 1'b0;
S3: detected = 1'b0;
S4: detected = 1'b0;
S5: detected = 1'b0;
S6: detected = 1'b1;
default: detected = 1'b0;
endcase
end

endmodule

C.

module tb_moore;

// Inputs

reg clk;

reg data_in;

reg reset;

// Outputs

wire detected;

// Instantiate the Unit Under Test (UUT)

moore_detector uut (

.clk(clk),

.data_in(data_in),

.reset(reset),

.detected(detected)

);

initial begin

// Initialize Inputs

clk = 0;

data_in = 0;

reset = 1;

// Wait 100 ns for global reset to finish

#100;

  

// Add stimulus here

end

always begin

#10 clk = ~clk;

end

always begin

reset = 1'b0;

data_in = 1'b0;

#20;

data_in = 1'b1;

#20;

data_in = 1'b0;

#20;

data_in = 1'b1;

#20;

data_in = 1'b0;

#20;

data_in = 1'b1;

#20;

data_in = 1'b0;

#20;

data_in = 1'b0;

#20;

data_in = 1'b0;

#20;

end

  

endmodule