Question
In: Electrical Engineering
Write the VERILOG code for an arithmetic/logic unit (ALU) following , and can be tested in...
Write the VERILOG code for an arithmetic/logic unit (ALU) following , and can be tested in on nexys 4 board
This is to be implement on : ISE Design Suite - Xilinx
/* ALU Arithmetic and Logic Operations ---------------------------------------------------------------------- |ALU_Sel| ALU Operation ---------------------------------------------------------------------- | 0000 | ALU_Out = A + B; ---------------------------------------------------------------------- | 0001 | ALU_Out = A - B; ---------------------------------------------------------------------- | 0010 | ALU_Out = A * B; ---------------------------------------------------------------------- | 0011 | ALU_Out = A / B; ---------------------------------------------------------------------- | 0100 | ALU_Out = A << 1; ---------------------------------------------------------------------- | 0101 | ALU_Out = A >> 1; ---------------------------------------------------------------------- | 0110 | ALU_Out = A rotated left by 1; ---------------------------------------------------------------------- | 0111 | ALU_Out = A rotated right by 1; ---------------------------------------------------------------------- | 1000 | ALU_Out = A and B; ---------------------------------------------------------------------- | 1001 | ALU_Out = A or B; ---------------------------------------------------------------------- | 1010 | ALU_Out = A xor B; ---------------------------------------------------------------------- | 1011 | ALU_Out = A nor B; ---------------------------------------------------------------------- | 1100 | ALU_Out = A nand B; ---------------------------------------------------------------------- | 1101 | ALU_Out = A xnor B; ---------------------------------------------------------------------- | 1110 | ALU_Out = 1 if A>B else 0; ---------------------------------------------------------------------- | 1111 | ALU_Out = 1 if A=B else 0;
Solutions
Expert Solution
Thus we have listed the verilog code for the ALU which performs 16 different operations which can be selected using 4 bit Alu_sel input.
Manojponduru answered 11 months agoRelated Solutions
write an Arithmetic Logic Unit (ALU) in verilog.
write an Arithmetic Logic Unit (ALU) in verilog.
Write the VERILOG code for an arithmetic/logic unit (ALU) with a test bench that does the...
Write the VERILOG code for an arithmetic/logic unit (ALU) with a
test bench that does the following with 4 bit inputs , and can be
tested in on nexys 4 board
This is to be implement on : ISE Design Suite - Xilinx
/* ALU Arithmetic and Logic Operations
----------------------------------------------------------------------
|ALU_Sel| ALU Operation
----------------------------------------------------------------------
| 0000 | ALU_Out = A + B;
----------------------------------------------------------------------
| 0001 | ALU_Out = A - B;
----------------------------------------------------------------------
| 0010 | ALU_Out = A * B;...
The heart of a computer system is an ARITHMETIC AND LOGIC UNIT (ALU) which is responsible...
The heart of a computer system is an ARITHMETIC AND
LOGIC UNIT (ALU) which is responsible for executing arithmetic
(e.g., addition, subtraction, etc.) and logic (e.g., AND, OR, etc.)
operations. In this project, you will design, simulate, and
implement a simple 1-bit ALU.
The truth table for ALU is given below:
Operation Selection Inputs Operation Output(s)
S0 S1 A B
0 0 A AND B AB
0 1 A NOR B (A+B)’
1 0 A XNOR B (A⊕B)’
1 1...
draw state machine and write verilog code of an ALU unit that shifts left when the...
draw state machine and write verilog code of an ALU unit that
shifts left when the control signal 'OP' is 00, shifts right when
control is ''01'' and increments when control is ''10''. Fpr
control ''11'' , it does nothing. inputs are Date [3:0] and clk,
and the output is Out [3:0]
use modelsim write Verilog code for the following digital logic circuits and then simulate them by...
use modelsim write Verilog code for the following digital logic
circuits and then simulate them by writing a testbench module for
each of them ,
(a)The FSMs for the snail problem that is in the slides (a snail
crawls over a tape that has 0 and 1 and smiles if it has detected
the '10' bits using both Moore and Mealy FSM. Note that the pattern
is '10' not '01' as in the slides.
(b) A rock-paper-scissor game played by...
1. a) Given the two Verilog code segments, derive the schematics for the logic that will...
1. a) Given the two Verilog code segments, derive the schematics
for the logic that will be synthesized from these blocks.
BLOCK 1
input Y;
reg A, B;
always @(posedge clk)
begin
A = Y;
B = A;
end
BLOCK 2
input Y;
reg A, B;
always @(posedge clk)
begin
A <= Y;
B <= A;
end
b) Define setup time by using timing diagrams. Explain what
would happen if any one of these timing requirements are
violated.
c) Describe...
Write VHDL code for ALU 32bit. ALU must perform addition and subtraction. You are not allowed...
Write VHDL code for ALU 32bit. ALU must perform addition and
subtraction. You are not allowed to use
other libraries. Only this libraries are allowed to
use:
use library ieee;
use ieee.std_logic_1164.all;
Please do it correctly and include the comments
for me to fully understand. Thank you.
Write VHDL code for ALU 32bit. ALU must perform addition and subtraction. You are not allowed...
Write VHDL code for ALU 32bit. ALU must perform addition and
subtraction. You are not allowed to use other libraries only this
is allowed to use library ieee; use ieee.std_logic_1164.all; Please
write the comments for me to fully understand. Thank you.
Can anyone write a Verilog code and a test bench for a universal shift register with...
Can anyone write a Verilog code and a test bench for a universal
shift register with 4 bits using D flip flop? Thanks
Analyze the following Verilog code and write down its output as pictured in the code. module...
Analyze the following Verilog code and write
down its output as pictured in the code.
module blocking;
reg [0:7] A, B;
initial begin: init1
A = last decimal digit of your ID;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;
$display("Output 1: A= %b B= %b", A, B );
A = last decimal digit of your ID;
#1 A <= A + 1;
B <= A + 1;
#1 $display ("Output 2: A=...
ADVERTISEMENT
ADVERTISEMENT
Latest Questions
- Discuss the significance of a proposal What elements do you think are needed for the proposal...
- 1) Given the following equations: QD = 5,000 + 0.5 I + 0.2 A -...
- How has the Supreme Court's Citizens United decision changed campaigns in America? (long answer is appreciated...
- You are a Derivatives Trader at a major Broker-Dealer. At the end of the week you...
- What are the two reasons that limit the ability of correlational studies to provide information on...
- Suppose that 20 monthly payments of $100 each are followed by 30 monthly payments of $200...
- D. Explain what it means for recommendations to be specific and actionable. E. Discuss how charts...
ADVERTISEMENT