Question

In: Electrical Engineering

Write down the VERILOG code for an XOR gate and the testbench code to test it

Write down the VERILOG code for an XOR gate and the testbench code to test it

Solutions

Expert Solution


XOR GATE

Verilog design

//in Structural model

module xor_gate (
input a,b,
output y);

   xor x1(y,a, b);

endmodule

TestBench

module tb_and_gate;

    reg A,B;
    wire Y;
    
    xor_gate a1 (.a(A) ,.b(B),.y(Y));         
    
    initial begin
    
        A =1'b0;
        B= 1'b0;
        #45 $finish;
    
    end     
    
    always #6 A =~A;
    always #3 B =~B;
    
    always @(Y)
    $display( "time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value Y =%b",$time,A,B,Y);

endmodule

output

time =0         INPUT VALUES:    A=0 B =0        output value Y =0
time =3         INPUT VALUES:    A=0 B =1        output value Y =1
time =6         INPUT VALUES:    A=1 B =0        output value Y =1
time =9         INPUT VALUES:    A=1 B =1        output value Y =0

Related Solutions

Please write down in Verilog code with testbench: Audio Tone Generator like Ambulance siren or Police...
Please write down in Verilog code with testbench: Audio Tone Generator like Ambulance siren or Police siren.
Please Create the Verilog/Vivado Code For: An LFSR Pseudonumber generator, and the testbench for test it,...
Please Create the Verilog/Vivado Code For: An LFSR Pseudonumber generator, and the testbench for test it, please comment and explain the answer as much as possible if possible, post Pic of the waveform simulation!
Please Create the Verilog/Vivado Code For: An LFSR Pseudonumber generator, and the testbench for test it,...
Please Create the Verilog/Vivado Code For: An LFSR Pseudonumber generator, and the testbench for test it, please comment and explain the answer as much as possible waveform simulation answer would be nice too!
Please Create the Verilog/Vivado Code For: An LFSR Pseudonumber generator, and the testbench for test it,...
Please Create the Verilog/Vivado Code For: An LFSR Pseudonumber generator, and the testbench for test it, please comment and explain the answer as much as possible!
Please Create the Verilog/Vivado Code For: An LFSR Pseudonumber generator, and the testbench for test it,...
Please Create the Verilog/Vivado Code For: An LFSR Pseudonumber generator, and the testbench for test it, please comment and explain the answer as much as possible,(Make your own code, even it is more simple, but do not copy from others sources on the internet) if possible, post Pic of the waveform simulation!
Implement a 4x4 multiplier using gate level (verilog code and test bench)
Implement a 4x4 multiplier using gate level (verilog code and test bench)
Design and write a verilog code and testbench for a 16-bit RISC MIPS Processor on vivado...
Design and write a verilog code and testbench for a 16-bit RISC MIPS Processor on vivado and show waveform.
Design an 8-bit adder. Show Verilog code and testbench.
Design an 8-bit adder. Show Verilog code and testbench.
Verilog code for Traffic light controller. Need a block diagram, Verilog codes used with testbench, and...
Verilog code for Traffic light controller. Need a block diagram, Verilog codes used with testbench, and the waveforms screen-prints.
Verilog code to make 8bit bcd to 8bit binary please with testbench
Verilog code to make 8bit bcd to 8bit binary please with testbench
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT