Question

In: Electrical Engineering

Write down the VERILOG code for an XOR gate and the testbench code to test it

Write down the VERILOG code for an XOR gate and the testbench code to test it

Solutions

Expert Solution


XOR GATE

Verilog design

//in Structural model

module xor_gate (
input a,b,
output y);

   xor x1(y,a, b);

endmodule

TestBench

module tb_and_gate;

    reg A,B;
    wire Y;
    
    xor_gate a1 (.a(A) ,.b(B),.y(Y));         
    
    initial begin
    
        A =1'b0;
        B= 1'b0;
        #45 $finish;
    
    end     
    
    always #6 A =~A;
    always #3 B =~B;
    
    always @(Y)
    $display( "time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value Y =%b",$time,A,B,Y);

endmodule

output

time =0         INPUT VALUES:    A=0 B =0        output value Y =0
time =3         INPUT VALUES:    A=0 B =1        output value Y =1
time =6         INPUT VALUES:    A=1 B =0        output value Y =1
time =9         INPUT VALUES:    A=1 B =1        output value Y =0

Manojponduru answered 2 years ago
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