Question

create a test bench for the following code:

module signed_mult (out, clk, a, b);
output [15:0] out;
input clk;
input signed [7:0] a;
input signed [7:0] b;
reg signed [7:0] a_reg;
reg signed [7:0] b_reg;
reg signed [15:0] out;
wire signed [15:0] mult_out;
assign mult_out = a_reg * b_reg;
always@(posedge clk)
begin
a_reg <= a;
b_reg <= b;
out <=mult_out;
end
endmodule

Answer 1

Ans:

The testbench:

// Code your testbench here
// or browse Examples
module test();
reg clk;
reg signed [7:0] a,b;
wire signed [15:0] out;
integer i;
signed_mult m1(out,clk,a,b);
initial
begin
clk=0;
#2
for(i=0;i<=5;i++)// the number can be incremented and -negative numbers can be added as well
begin
#4 a=i;b=i;
if(out != a*b)
begin
$display("out=%b a=%b b=%b, time =%0d",out,a,b,$time);
$display("fail");
end
else
begin
$display("out=%b a=%b b=%b,, time =%0d",out,a,b,$time);
$display("OK");
end
end
#30 $finish;
end
initial
forever
#2 clk=~clk;
//initial
//$monitor("out=%b a=%b b=%b",out,a,b);
endmodule

output:

out=xxxxxxxxxxxxxxxx a=00000000 b=00000000,, time =6
OK
out=xxxxxxxxxxxxxxxx a=00000001 b=00000001,, time =10
OK
out=0000000000000000 a=00000010 b=00000010, time =14
fail
out=0000000000000001 a=00000011 b=00000011, time =18
fail
out=0000000000000100 a=00000100 b=00000100, time =22
fail
out=0000000000001001 a=00000101 b=00000101, time =26
fail
Done

Note: the design is working incorretly the output is 2 cycles delayed by the corresponding input hence causing the fails to occur. fix the design for flaws