Question

The goal in this experiment is to implement a 0-12 counter with a test bench that displays the output of each of the flip-flops in the counter. A behavioral code should be written for this experiment.

Set the time format to 1 nanosecond with a precision of 100 picosecond.

Answer 1

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UP_COUNTER is
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end UP_COUNTER;
architecture Behavioral of UP_COUNTER is
signal counter_up: std_logic_vector(3 downto 0);
begin
-- up counter
process(clk,reset)
begin
if(rising_edge(clk)) then
if(reset='1' or counter_up="1100") then
counter_up <= x"0";
else
counter_up <= counter_up + x"1";
end if;
end if;
end process;
counter <= counter_up;
end Behavioral;
TEST BENCH FOR VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench  
-- VHDL project: Testbench VHDL code for up counter
entity tb_counters is
end tb_counters;
architecture Behavioral of tb_counters is
component UP_COUNTER
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end component;
signal reset,clk: std_logic;
signal counter:std_logic_vector(3 downto 0);
begin
dut: UP_COUNTER port map (clk => clk, reset=>reset, counter => counter);
-- Clock process definitions
clock_process :process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc: process
begin   
-- hold reset state for 100 ns.
reset <= '1';
wait for 20 ns;   
reset <= '0';
wait;
end process;
end Behavioral;
The screen shot of the testbench simulation is given below:

Verilog code:

module mod13_vlog(
out , // Output of the counter
clk , // clock input
reset // reset input
);
//----------Output Ports--------------
output [3:0] out;
//------------Input Ports--------------
input clk, reset;
//------------Internal Variables--------
reg [3:0] out;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset)
begin // active high reset
out <= 3'b0 ;
end
else if (out<12)
begin
out <= out + 1;
end
else
begin
out <= 3'b0 ;
end
endmodule
Verilog Test bench:
`timescale 1ns/100ps
module tb_mod13_vlog;
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] out;
// Instantiate the Unit Under Test (UUT)
mod13_vlog uut (
.out(out),
.clk(clk),
.reset(reset)
);
initial begin
clk=1'b1;
forever #5 clk=~clk;
end

initial begin
$monitor($time," out=%h q[0]=%b q[1]=%b q[2]=%b q[3]=%b ",out,out[0],out[1],out[2],out[3]);
reset = 1;#10;
reset = 0;#30;
  
end

endmodule
The screen shot of the testbench results is given below: