Question

Can someone create a Test bench for this 4 Bit USR code so that it can shift left, shift right and Load. This is in VHDL. Please type out the code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Uni_reg is
port( LR,SP,clk,clear,shL,shR: in std_logic; -- shL = shift left shR= shift right
Da,Db,Dc : in std_logic; --inputs for load
Qa,Qb,Qc : out std_logic); --out puts from the flipflops
end Uni_reg;

architecture Structural of Uni_reg is

signal lr1,lr2,sp1,sp2,R1,R2,R3 : std_logic;
signal L1,L2,L3,LOAD1,LOAD2,LOAD3:std_logic;
signal c1,c2,c3 : std_logic;
signal Qas,Qbs,Qcs : std_logic;

component andgate
port(a,b,c : in std_logic; z : out std_logic);
end component;

component orgate
port(a,b,c : in std_logic; z : out std_logic);
end component;

component notgate
port(a: in std_logic; z : out std_logic);
end component;

component Dflipflop
port(D,clk: in std_logic; Q: out std_logic);
end component;

begin

NOTGATE1: notgate port map (LR,lr1);--1st notgate for LEFT/RIGHT
NOTGATE2: notgate port map (lr1,lr2);--2nd notgate for LEFT/RIGHT
NOTGATE3: notgate port map (SP,sp1);--1st notgate for SERIAL/PARRALLEL
NOTGATE4: notgate port map (sp1,sp2);--2nd notgate for SERIAL/PARRALLEL

ANDGATE1: andgate port map (shR,sp2,lr2,R1); --for right shift of 1st bit
ANDGATE2: andgate port map (sp2,lr1,Qbs,L1); --for left shift of 1st bit
ANDGATE3: andgate port map (lr2,sp1,Da,LOAD1);--for load of 1st bit
ANDGATE4: andgate port map (Qas,sp2,lr2,R2); --for right shift of 2nd bit
ANDGATE5: andgate port map (sp2,lr1,Qcs,L2); --for left shift of 2nd bit
ANDGATE6: andgate port map (lr2,sp1,Db,LOAD2);--for load of 2nd bit
ANDGATE7: andgate port map (Qbs,sp2,lr2,R3); --for right 3rd bit
ANDGATE8: andgate port map (sp2,lr1,shL,L3); --for left 3rd bit
ANDGATE9: andgate port map (lr2,sp1,Dc,LOad3);--for loading 3rd bit

ORGATE1: orgate port map (R1,L1,LOAD1,c1);--for the 1st flipflop
ORGATE2: orgate port map (R2,L2,LOAD2,c2);--for the 2nd flipflop
ORGATE3: orgate port map (R3,L3,LOAD3,c3);--for the 3rd flipflop

FLIPFLOP1: Dflipflop port map (c1,clk,Qas);
FLIPFLOP2: Dflipflop port map (c2,clk,Qbs);
FLIPFLOP3: Dflipflop port map (c3,clk,Qcs);

process(clk,clear)
begin
if clear ='1' then
c1<='0';
elsif (clk'event and clk = '1') then
c1<=c1;
Qa <= c1;
end if;
end process;

process(clk,clear)
begin
if clear ='1' then
Qbs<='0';
elsif (clk'event and clk = '1') then
Qbs<= Qbs;
Qb <= Qbs;
end if;
end process;

process(clk,clear)
begin
if clear ='1' then
Qcs<='0';
elsif (clk'event and clk = '1') then
Qcs<=Qcs;
Qc <= Qcs;
end if;
end process;

end Structural;

Answer 1

--VHDL TestBench

library IEEE;

use IEEE.Std_logic_1164.all;

use IEEE.Numeric_Std.all;

entity Uni_reg_tb is

end;

architecture bench of uni_reg_tb is

component Uni_reg

port( LR,SP,clk,clear,shL,shR:in std_logic;

Da,Db,Dc : in std_logic;

Qa,Qb,Qc : out std_logic);

end component ;

signal LR,SP,clk,clear,shL,shR:std_logic;

signal Da,Db,Dc: std_logic;

signal qa,Qb,Qc: std_logic;

constant clock_period :time:-10n ;

signal stop_the _clock :boolean;

begin

uut: Uni_reg port map ( LR =>LR,

SP =>SP,

clk => clk,

clear => clear,

shL => shL,

shR =>shR,

Da => Da,

Db => Db,

Dc => Dc,

Qa => Qa,

Qb => Qb,

Qc => Qc);

stimulus : process

begin

-- put initialization code here

clear <='1' ;

wait for 5 ns;

clear <='0' ;

wait for 5 ns;

--Put test bech stimulus code here

stop_the_clock <=true;

wait;

end process;

clocking:process

begin

while not stop_the_clock loop

clk <='0', '1' after clock_period/2;

wait for clock_period;

end loop;

wait;

end process;

end ;

--configuration declaration

configuration cfg_Uni_reg_tb of Uni_reg_tb is  

for bench

for uut: Uni_reg

--default configuration

end for;

end for;

end cfg_Uni_reg_tb ;

configuration cfg_Uni_reg_tb_Structural of Uni_reg_tb is

for bench

for uut: uni_reg

use entity work.Uni_reg(Structural);

end for ;

end for;

end cfg_Uni_reg_tb_Structural;