Question

module traffic(clk, reset, P1, P2, P3, P4, PL);
input clk;
input reset;
output[4:0] P1;
output[4:0] P2;
output[4:0] P3; // four roads
output [4:0] P4;
output[3:0] PL; //Pl is pedestrian

reg [4:0] P1;
reg [4:0] P2;
reg [4:0] P3;
reg [4:0] P4;
reg [3:0] PL;
reg [4:0] sig;

always @(posedge clk or negedge reset)
begin
   if(reset == 1'b0)begin
       P1 <= 5'b00100;
       P2 <= 5'b00100;
       P3 <= 5'b00100;
       P4 <= 5'b00100;
       PL <= 4'b1111;
       sig <= 5'b00000;
   end
   else begin
       sig <= sig + 1;
      
       case(sig[4:0])
       5'b00000:begin
       P1 <= 5'b10011; //path 1 is greeen
       P2 <= 5'b00100; //all other paths are red
       P3 <= 5'b10011;
       P4 <= 5'b10011;
       PL <= 4'b1111;
       end
      
       5'b00100:begin
       P1 <= 5'b01000; //path 1 is yellow
       P2 <= 5'b00100; // all other paths are red
       P3 <= 5'b00100;
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b01000:begin
       P1 <= 5'b00100; //path 1 is red
       P2 <= 5'b10011; //path 2 is green
       P3 <= 5'b00100; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b01100:begin
       P1 <= 5'b00100;
       P2 <= 5'b01000; //path 2 is yellow
       P3 <= 5'b00100; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b10000:begin
       P1 <= 5'b00100;
       P2 <= 5'b00100; //path 3 is green
       P3 <= 5'b10011; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b10100:begin
       P1 <= 5'b00100;
       P2 <= 5'b00100; //path 3 is yellow
       P3 <= 5'b01000; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b11000:begin
       P1 <= 5'b00100;
       P2 <= 5'b00100; //all other paths are red
       P3 <= 5'b00100; // path 4 is yello
       P4 <= 5'b10011;
       PL <= 4'b1111;
       end

       5'b11100:begin
       P1 <= 5'b00100; //all other paths are red
       P2 <= 5'b00100;
       P3 <= 5'b00100;
       P4 <= 5'b00100;
       PL <= 4'b0000; //pedestrian green
       end

       5'b11111:sig<= 6'b00000;

       default:begin     
      
       end
   endcase

   end
end

endmodule

can anyone write a testbench for this code in Verilog.

Answer 1

TESTBENCH FOR THE GIVEN CODE:

module testbench_traffic;

reg clk;
reg reset;
wire [4:0] P1;
wire [4:0] P2;
wire [4:0] P3; // four roads
wire [4:0] P4;
wire [3:0] PL; //Pl is pedestrian
wire [4:0] sig;

initial begin clk=1'b0;reset=1'b0; end //since clk and reset are reg types,we are giving initial values
always #10 clk=~clk; //generate clock with time period 20ns
always #200 reset=~reset; //generate reset with some time period
traffic k(clk, reset, P1, P2, P3, P4, PL); //instantiate the module traffic

  

endmodule

EXPLANATION:

To write a test bench code

1.create a simulaton source.

2.declare all inputs as reg types.

3. declare all outputs as wire type.

4.give initial values to reg type inputs.

5.generate clock ,.

6.generate reset pulse.

6.instantiate the module,

7.use initial block again to change the values of the inputs with some delays,if needed

CODE:

SIMULATION WAVEFORMS: