Question
In: Electrical Engineering
module traffic(a, b,clk, reset, P1, P2, PL1, PL2, ind); input a,b; input clk; //g=100 y=010 r=001...
module traffic(a, b,clk, reset, P1, P2, PL1, PL2, ind);
input a,b;
input clk; //g=100 y=010 r=001
input reset; //g for pedes = 000 red = 111
input ind;
output[2:0] P1;
output[2:0] P2; // two roads
output[1:0] PL1; //Pl is pedestrian
output[1:0] PL2;
reg [2:0] P1;
reg [2:0] P2;
reg [1:0] PL1;
reg [1:0] PL2;
reg [2:0] sig;
always @(posedge clk, posedge reset)
if(reset)
begin
P1 <= 3'b100;
P2 <= 3'b001;
PL1 <= 3'b111;
PL2 <= 3'b000;
end
else begin
// pass the next_state to current_state;
sig <= sig + 1;
case(sig[2:0])
3'b000:begin
P1 <= 3'b100; //path 1 is greeen
P2 <= 3'b001; //path 2 is red
PL1 <= 3'b111;
PL2 <= 3'b000;
end
3'b001:begin
P1 <= 3'b010; //path 1 is yellow
P2 <= 3'b001; // path 2 is red
PL1 <= 3'b000;
PL2 <= 3'b111;
end
3'b010:begin
P1 <= 3'b001; //path 1 is red
P2 <= 3'b100; //path 2 is green
PL1 <= 3'b000;
PL2 <= 3'b111;
end
3'b011:begin
P1 <= 5'b001; //path 1 is red
P2 <= 5'b010; //path 2 is yellow
PL1 <= 3'b000;
PL2 <= 3'b111;
end
3'b100:begin
P1 <= 3'b001; //path 1 is red
P2 <= 3'b001; //path 3 is red
PL1 <= 3'b000;
PL2 <= 3'b000;
end
5'b11111:sig<= 6'b00000;
default:begin
end
endcase
end
endmodule
Can anyone write a testbench for this in Verilog, ind means indicator.
Solutions
Expert Solution
// the design has flaws a,b,ind are not used in the behavious of
the design
// sig was no initialised hence the design wont work
// fixed the second flaw
module traffic(a, b,clk, reset, P1, P2, PL1, PL2, ind);
input a,b;
input clk; //g=100 y=010 r=001
input reset; //g for pedes = 000 red = 111
input ind;
output[2:0] P1;
output[2:0] P2; // two roads
output[1:0] PL1; //Pl is pedestrian
output[1:0] PL2;
reg [2:0] P1;
reg [2:0] P2;
reg [1:0] PL1;
reg [1:0] PL2;
reg [2:0] sig;
always @(posedge clk, posedge reset)
if(reset)
begin
P1 <= 3'b100;
P2 <= 3'b001;
PL1 <= 3'b111;
PL2 <= 3'b000;
sig<=0;// design was flawed i used this to fic you design
flaws
end
else begin
// pass the next_state to current_state;
sig <= sig + 1;
case(sig[2:0])
3'b000:begin
P1 <= 3'b100; //path 1 is greeen
P2 <= 3'b001; //path 2 is red
PL1 <= 3'b111;
PL2 <= 3'b000;
end
3'b001:begin
P1 <= 3'b010; //path 1 is yellow
P2 <= 3'b001; // path 2 is red
PL1 <= 3'b000;
PL2 <= 3'b111;
end
3'b010:begin
P1 <= 3'b001; //path 1 is red
P2 <= 3'b100; //path 2 is green
PL1 <= 3'b000;
PL2 <= 3'b111;
end
3'b011:begin
P1 <= 5'b001; //path 1 is red
P2 <= 5'b010; //path 2 is yellow
PL1 <= 3'b000;
PL2 <= 3'b111;
end
3'b100:begin
P1 <= 3'b001; //path 1 is red
P2 <= 3'b001; //path 3 is red
PL1 <= 3'b000;
PL2 <= 3'b000;
end
5'b11111:sig<= 6'b00000;
default:begin
end
endcase
// $display("sig=%b ",sig);
end
endmodule
//////testbench:
module test();
reg a,b,clk,reset,ind;
wire [2:0] P1,P2;
wire [1:0] PL1,PL2;
traffic t1(.*);// .* automatic connection if the name of the ports
are same as variable names in the testbench
initial
begin
clk=0;reset=0;a=0;b=0;ind=0;
#2 reset=1;
#4 reset=0;
#40
#4 a=0;b=0;ind=1;
#40 $finish;
end
initial
forever
#2 clk=~clk;
initial
begin
$monitor("a=%b b=%b ind=%b reset=%b P1=%b p2=%b PL1=%b
PL2=%b",a,b,ind,reset,P1,P2,PL1,PL2);
end
endmodule
output:
19-12-03 00:35:02 EST] iverilog '-Wall' '-g2012' design.sv
testbench.sv && unbuffer vvp a.out
a=0 b=0 ind=0 reset=0 P1=xxx p2=xxx PL1=xx PL2=xx
a=0 b=0 ind=0 reset=1 P1=100 p2=001 PL1=11 PL2=00
a=0 b=0 ind=0 reset=0 P1=100 p2=001 PL1=11 PL2=00
a=0 b=0 ind=0 reset=0 P1=010 p2=001 PL1=00 PL2=11
a=0 b=0 ind=0 reset=0 P1=001 p2=100 PL1=00 PL2=11
a=0 b=0 ind=0 reset=0 P1=001 p2=010 PL1=00 PL2=11
a=0 b=0 ind=0 reset=0 P1=001 p2=001 PL1=00 PL2=00
a=0 b=0 ind=0 reset=0 P1=100 p2=001 PL1=11 PL2=00
a=0 b=0 ind=0 reset=0 P1=010 p2=001 PL1=00 PL2=11
a=0 b=0 ind=0 reset=0 P1=001 p2=100 PL1=00 PL2=11
a=0 b=0 ind=1 reset=0 P1=001 p2=010 PL1=00 PL2=11
a=0 b=0 ind=1 reset=0 P1=001 p2=001 PL1=00 PL2=00
a=0 b=0 ind=1 reset=0 P1=100 p2=001 PL1=11 PL2=00
a=0 b=0 ind=1 reset=0 P1=010 p2=001 PL1=00 PL2=11
a=0 b=0 ind=1 reset=0 P1=001 p2=100 PL1=00 PL2=11
a=0 b=0 ind=1 reset=0 P1=001 p2=010 PL1=00 PL2=11
a=0 b=0 ind=1 reset=0 P1=001 p2=001 PL1=00 PL2=00
Done
Manojponduru answered 1 year agoRelated Solutions
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