Question

can i ask FSM verilog?

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module FSM(clk, rst, choice, out);

input clk, rst, choice; output reg [1:0] out;

reg [1:0] state, nextstate;
parameter [1:0] S0 = 2’b00, S1 = 2’b01,

S2 = 2’b10, S3 = 2’b11;

always@(posedge clk) begin

if (rst == 1’b0) begin

state <= S0;

end else

end state <= nextstate;

always@(state, rst, choice) begin

case (state) S0 : begin

out = 2’b00;

if (rst == 1’b1) nextstate <= S1; end

S1 : begin
out = 2’b01;
if (choice == 1’b1) nextstate <= S2; else nextstate <= S3;

end

S2 : begin
out = 2’b10;
if (rst == 1’b1) nextstate <= S0;

end

S3 : begin
out = 2’b11;
if (rst == 1’b1) nextstate <= S0;

end endcase

end endmodule

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Q) i knew this kind of fsm verilog code contain sequen, comb logic

how can i rewrite that code with seq + comb+ output logic?

Answer 1

// Code your design here
module FSM(clk, rst, choice, out);
input clk, rst, choice;
output reg [1:0] out;

reg [1:0] state, nextstate;
parameter [1:0] S0=0, S1 =1,S2 =2, S3 =3;
  
// reset block sequntial block for state transition

always@(posedge clk)
begin
if(!rst)
begin
state <= S0;
end
else
state <= nextstate;
end
  
// block combinational for next state determination
always@(state, rst, choice)
begin
case (state)
S0 :
begin
  
if (rst) nextstate <= S1;
end
S1 :
begin
  
if (choice) nextstate <= S2; else nextstate <= S3;
end
S2 :
begin
  
if (rst) nextstate <= S0;
end
S3 : begin
  
if (rst) nextstate <= S0;
end
endcase
end
  
  
// output block combinational
always@(state)
begin
case (state)
S0 :
begin
out =0;
end
S1 :
begin
out =1;
end
S2 :
begin
out = 2;
  
end
S3 : begin
out = 3;
end
endcase
end
endmodule

note: the code that you have written is also divided into two parts

the reset part with posedge clock will work as sequential block.

since.

FSM has two combinational of blocks.

1 combination block for Flip flop excitation

second for output.

the sequential block will just take the outputs of the combination excitation block and just buffer it to output according to sequential logic.