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Write Verilog code using for 3:8 Decoders with Quartus-II CAD software?? and write code of Full...

Write Verilog code using for 3:8 Decoders
with Quartus-II CAD software??
and write code of Full adder using 2 half adder ?

Solutions

Expert Solution

5

module decoder3to8 (input [2:0] I, output reg [7:0] Y);

always @ (I) begin

case (I)
3'b000: Y <= 8'b00000001;
3'b001: Y <= 8'b00000010;
3'b010: Y <= 8'b00000100;
3'b011: Y <= 8'b00001000;
3'b100: Y <= 8'b00010000;
3'b101: Y <= 8'b00100000;
3'b110: Y <= 8'b01000000;
3'b111: Y <= 8'b10000000;
default: Y <= 8'b00000000;
endcase

end

endmodule

Q2 (a)

module half_adder (input x, y, output sum, carry);

assign sum = x ^ y;
assign carry = x & y;

endmodule

///

(b)

module full_adder (input x, y, cin, output sum, cout);

wire [2:0] w;

half_adder u0 (x, y, w[0], w[1]);
half_adder u1 (w[0], cin, sum, w[2]);

assign cout = w[1] | w[2];

endmodule

///////////

venereology answered 6 months ago
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