Question

Currently, this model detects the overlapping sequence "101" ----> REDESIGN the Moore FSM below to detect the NEW sequence "011" , simulate using the same test bench, and create a Moore Transition Diagram for the new sequence 011.

module moore_seq
(
   input clock, reset, x,
   output reg z
);
//assign binary encoded codes to the states A through D
parameter
   A = 2'b00,
   B = 2'b01,
   C = 2'b10,
   D = 2'b11;
reg [1 : 0] current_state, next_state;

//Section 1: Next state generator (NSG)
always@(*)
begin
   casex (current_state)

   A: if ( x == 1)
       next_state = B;

   else

       next_state = A;

   B: if (x ==1)
       next_state = B;

   else

       next_state = C;

   C: if (x == 1)
       next_state = D;

   else

       next_state = A;

   D: if (x == 1)
       next_state = B;

   else

       next_state = C;

   endcase
end

//Section 2: Output generator
always@(*)
begin
   if (current_state == D)
       z = 1;
   else
       z = 0;
end

//Section 3: The Flip-flops
always@(posedge clock, posedge reset)
begin
   if (reset == 1)
       current_state <= A;

   else

       current_state <= next_state;
   end

endmodule

// This the test bench

`include "moore_seq.v"

module moore_seq_tb();

reg clock, reset, x;

wire z;

moore_seq u1(clock, reset, x, z);

initial begin
$monitor("%4d: z = %b", $time, z);
clock = 0;
reset = 1;
x = 0;
#10 reset = 0;
end

always begin
#5clock = ~clock;
end

initial begin

#10 x = 1; $display("%4d: x = %b", $time, x);
#10 x = 1; $display("%4d: x = %b", $time, x);
#10 x = 1; $display("%4d: x = %b", $time, x);
#10 x = 0; $display("%4d: x = %b", $time, x);
#10 x = 1; $display("%4d: x = %b", $time, x);
#10 x = 0; $display("%4d: x = %b", $time, x);
#10 x = 1; $display("%4d: x = %b", $time, x);
#10 x= 1; $display("%4d: x = %b", $time, x);
#10 x = 0; $display("%4d: x = %b", $time, x);
#10 x= 0; $display("%4d: x = %b", $time, x);
#10 $finish;
end
endmodule

Answer 1

//verilog code for 011 moore FSM

module moore_seq

(

input clock, reset, x,

output reg z

);

//assign binary encoded codes to the states A through D

parameter

A = 2'b00,

B = 2'b01,

C = 2'b10,

D = 2'b11;

reg [1 : 0] current_state, next_state;

//Section 1: Next state generator (NSG)

always@(*)

begin

casex (current_state)

A: if ( x == 1)

next_state = A;

else

next_state = B;

B: if (x ==1)

next_state = C;

else

next_state = B;

C: if (x == 1)

next_state = D;

else

next_state = B;

D: if (x == 1)

next_state = A;

else

next_state = B;

endcase

end

//Section 2: Output generator

always@(*)

begin

if (current_state == D)

z = 1;

else

z = 0;

end

//Section 3: The Flip-flops

always@(posedge clock, posedge reset)

begin

if (reset == 1)

current_state <= A;

else

current_state <= next_state;

end

endmodule

// This the test bench

'include "design.sv"

module moore_seq_tb();

reg clock, reset, x;

wire z;

moore_seq u1(clock, reset, x, z);

initial begin

$monitor("%4d: z = %b", $time, z);

clock = 0;

reset = 1;

x = 0;

#10 reset = 0;

end

always begin

#5clock = ~clock;

end

initial begin

#10 x = 1; $display("%4d: x = %b", $time, x);

#10 x = 1; $display("%4d: x = %b", $time, x);

#10 x = 1; $display("%4d: x = %b", $time, x);

#10 x = 0; $display("%4d: x = %b", $time, x);

#10 x = 1; $display("%4d: x = %b", $time, x);

#10 x = 0; $display("%4d: x = %b", $time, x);

#10 x = 1; $display("%4d: x = %b", $time, x);

#10 x= 1; $display("%4d: x = %b", $time, x);

#10 x = 0; $display("%4d: x = %b", $time, x);

#10 x= 0; $display("%4d: x = %b", $time, x);

#10 $finish;

end

endmodule

// Simulation waveforms