Question

Write a verilog code for 5 to 8 multiplier using fourbit adder

Answer 1

Verilog code

/*Half adder*/

module half_adder( input A, B,

                  output S, COUT );

       assign S = A^B;

       assign COUT = (A&B);

endmodule

/* Full adder*/

module full_adder( input A, B, CIN

                  output S, COUT );

       assign S = A^B^CIN;

       assign COUT = (A&B) | (CIN&(A^B));

endmodule

/* Four bit adder*/

module four_bit_adder( input [3:0] A, [3:0] B

                                       input C0,

                                       output [3:0] S,

                                       output C4);

wire C1,C2,C3;

    full_adder fa0 (A[0],B[0],C0,S[0],C1);

    full_adder fa1 (A[1],B[1],C1,S[1],C2);

    full_adder fa2 (A[2],B[2],C2,S[2],C3);

    full_adder fa3 (A[3],B[3],C3,S[3],C4);

endmodule

/* Top Module*/

module multiplier_5to8 (input [4:0] A,

     input [7:0] B,

     output [12:0] P);

wire t1,t2,t3,t4,t5,t6,t7,t8,t9,t10;

wire t11,t12,t13,t14,t15,t16,t17,t18,t19,t20;

wire t21,t22,t23,t24,t25,t26,t27,t28,t29,t30;

wire t31,t32,t33,t34,t35,t36,t37,t38,t39;

and(P[0],A[0],B[0]);

and(t1,A[0],B[1]);

and(t2,A[1],B[0]);

and(t3,A[0],B[2]);

and(t4,A[1],B[1]);

and(t5,A[2],B[0]);

and(t6,A[0],B[3]);

and(t7,A[1],B[2]);

and(t8,A[2],B[1]);

and(t9,A[3],B[0]);

and(t10,A[0],B[4]);

and(t11,A[1],B[3]);

and(t12,A[2],B[2]);

and(t13,A[3],B[1]);

and(t14,A[4],B[0]);

and(t15,A[0],B[5]);

and(t16,A[1],B[4]);

and(t17,A[2],B[3]);

and(t18,A[3],B[2]);

and(t19,A[4],B[1]);

and(t20,A[0],B[6]);

and(t21,A[1],B[5]);

and(t22,A[2],B[4]);

and(t23,A[3],B[3]);

and(t24,A[4],B[2]);

and(t25,A[0],B[7]);

and(t26,A[1],B[6]);

and(t27,A[2],B[5]);

and(t28,A[3],B[4]);

and(t29,A[4],B[3]);

and(t30,A[1],B[7]);

and(t31,A[2],B[6]);

and(t32,A[3],B[5]);

and(t33,A[3],B[4]);

and(t34,A[2],B[7]);

and(t35,A[3],B[6]);

and(t36,A[4],B[5]);

and(t37,A[3],B[7]);

and(t38,A[4],B[6]);

and(t39,A[4],B[7]);

half_adder ha0(P[1],C1,t1,t2);

four_bit_adder FB1(P[2],C2,C1, t3,t4, t5);

four_bit_adder FB2(S1,CA1, t6,t7, t8,t9);

half_adder ha1(P[3],C3,S1,C2);

four_bit_adder FB2(S2,CA2, t10,t11, t12,t13);

full_adder fa4 (P[4],C4,S2,t14,C3);

four_bit_adder FB3(S3,CA3, t15,t16, t17,t18);

full_adder fa5(P[5],C5,S3,t19,C4);

four_bit_adder FB4(S4,CA4, t20,t21, t22,t23);

full_adder fa6 (P[6],C6,S4,t24,C5);

four_bit_adder FB5(S5,CA5, t25,t26, t27,t28);

full_adder fa7 (P[7],C7,S5,t29,C6);

four_bit_adder FB6(S6,CA6, t30,t31, t32,t33);

half_adder ha2 (P[8],C8,S6,C7);

four_bit_adder FB7(P[9],C9, t34,t35, t36,C8);

full_adder fa8 (P[10],C10,t37,t38,C9);

half_adder ha3 (P[11],C11,t39,C10);

endmodule