Question

imulate/ code in verilog:

Develop an electronic key system using the FSM (moore) methology. Use from student ID and use the last 4 digits:(0864)

if the number is <5 then = 1

if the number is >=5 then = 0

example: 8012345. Take last 4 digits (2345) which makes it 0001.

In my case, the last 4 digits are 0864, which makes it 0110

features of FSM (moore FSM):

input 4 bits serially,

if the sequence is correct, then you proceed to next state. Otherwise, go to error state, then go to rest state

Answer 1

module fsm (input clock, X, output reg Z);

parameter REST=4'b0000, BIT1_C=4'b0001, BIT1_W=4'b0010, BIT2_C=4'b0011, BIT2_W=4'b0100, BIT3_C=4'b0101, BIT3_W=4'b0110, ERROR=4'b0111, NEXT=4'b1000; //define states

reg [3:0] current_state, next_state;

always @ (posedge clock)

begin

current_state <= next_state;

end

always @ (current_state, X)

begin

Z <= 1'b0; //output

case (current_state)

REST : if (X == 1'b0) //check for input '0'

next_state <= BIT1_C;

else

next_state <= BIT1_W;

BIT1_C : if (X == 1'b1) //check for input '1'

next_state <= BIT2_C;

else

next_state <= BIT2_W;

BIT1_W : next_state <= BIT2_W;

BIT2_C : if (X == 1'b1) //check for input '1'

next_state <= BIT3_C;

else

next_state <= BIT3_W;

BIT2_W : next_state <= BIT3_W;

BIT3_C : if (X == 1'b0) //check for input '0'

next_state <= NEXT;

else

next_state <= ERROR;

BIT3_W : next_state <= ERROR;

ERROR : next_state <= REST;

NEXT : Z <= 1'b1; // next_state <= REST; //uncomment this statement if design requires to reset after every successful key verification

default : next_state <= REST;

endcase

end

endmodule

//Simulation