Question

Design in VHDL a gray code decoder to excess 3 code

Screenshot the simulation and code.

Answer 1

VHDL code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity g_to_e is
port(g:in std_logic_vector(2 downto 0);
e:out std_logic_vector(3 downto 0));
end g_to_e;

architecture Behavioral of g_to_e is

begin
e(3)<=g(2) and ((not g(1)) or g(0));
e(2)<=((not g(2)) and g(0)) or (g(1) and (not(g(0))));
e(1)<=not g(0);
e(0)<= g(2) xnor (g(1) xor g(0));

end Behavioral;

simulation results