Question

VHDL Code will not run simulation. What is the problem with my code??

--VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DataMemory16Bits is
Port ( Address_DM : in STD_LOGIC_VECTOR(15 downto 0);
Data_In_DM : in STD_LOGIC_VECTOR(15 downto 0);
Clock : in STD_LOGIC;
We_DM : in STD_LOGIC;
Re_DM : in STD_LOGIC;
Data_Out_DM : out STD_LOGIC_VECTOR(15 downto 0));
end DataMemory16Bits;

architecture Behavioral of DataMemory16Bits is
Type DataMemory16Bits is array(0 to 31) of STD_LOGIC_VECTOR(15 downto 0);
signal memory: DataMemory16Bits;

begin
process (Address_DM, Clock, We_DM, Re_DM)
begin
Data_Out_DM <= (Others=>'Z');
if (Clock='1')
then
if We_DM='1' and Re_DM='0'
then
Memory(to_integer(unsigned(Address_DM))<= Data_In_DM;
end if;
if Re_DM='1' and We_DM='0'
then
Memory(to_integer(unsigned(Data_In_DM)<= Address_DM;
end if;
if Re_DM='1' and We_DM='1'
then
Data_Out_DM<=Memory(to_integer(unsigned(Address_DM);
else
Data_Out_DM<=(Others=>'Z');
end if;
end if;
end process;
end Behavioral;

Answer 1

-- See cooments with correct code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL; ---Include this library package

entity DataMemory16Bits is

Port ( Address_DM : in STD_LOGIC_VECTOR(15 downto 0);

Data_In_DM : in STD_LOGIC_VECTOR(15 downto 0);

Clock : in STD_LOGIC;

We_DM : in STD_LOGIC;

Re_DM : in STD_LOGIC;

Data_Out_DM : out STD_LOGIC_VECTOR(15 downto 0));

end DataMemory16Bits;

architecture Behavioral of DataMemory16Bits is

Type DataMemory16Bits is array(0 to 65535) of STD_LOGIC_VECTOR(15 downto 0);

-- Since ----address is 16 bit then locations will be 2*16 = 65536

signal memory: DataMemory16Bits;

begin

process (Address_DM, Clock, We_DM, Re_DM)

begin

Data_Out_DM <= (Others=>'Z');

if (Clock='1' and Clock'event)then --- Memory is always edge triggered. Event trigger causes false data write

if (We_DM='1' and Re_DM='0') then

Memory(conv_integer(Address_DM))<= Data_In_DM; --- use conv function and close brackets were --missing

end if;

if (Re_DM='1' and We_DM='0') then

Memory(conv_integer(Data_In_DM))<= Address_DM; --- use conv function and close brackets were - --missing

end if;

if (Re_DM='1' and We_DM='1')then

Data_Out_DM<=Memory(conv_integer(Address_DM)); --- use conv function and close brackets were --missing

else

Data_Out_DM<=(Others=>'Z');

end if;

end if;

end process;

end Behavioral;

---- Simulation on ModelSim