VHDL Code will not run simulation. What is the problem with my
code??
--VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity DataMemory16Bits is
Port ( Address_DM : in STD_LOGIC_VECTOR(15 downto 0);
Data_In_DM : in STD_LOGIC_VECTOR(15 downto 0);
Clock : in STD_LOGIC;
We_DM : in STD_LOGIC;
Re_DM : in STD_LOGIC;
Data_Out_DM : out STD_LOGIC_VECTOR(15 downto 0));
end DataMemory16Bits;
architecture Behavioral of DataMemory16Bits is
Type DataMemory16Bits is array(0 to 31) of STD_LOGIC_VECTOR(15
downto 0);
signal memory: DataMemory16Bits;
begin
process...
VHDL Code: Design a 16-bit 4-to-1 multiplexer using data-flow
implementation style. Data inputs and output should be 16-bit
vectors. In your test bench, you should include enough number of
test cases to show the correctness of your design.
Simulate this code in ISE Simulator (ISim) and screenshot the
simulation
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer is
Port (
din:in STD_LOGIC_VECTOR (7 downto 0);
sel:in STD_LOGIC_VECTOR (2 downto 0);
dout : out STD_LOGIC);
end multiplexer;
architecture Behavioral of multiplexer is
begin
process (din,sel)
begin
case sel is
when
"000"=> dout <= din(7);
when
"001"=> dout <= din(6);
when
"010"=> dout <= din(5);
when
"011"=>...
Write VHDL code (behavior model) to implement a 4-bit modulo-9
counter and simulate your VHDL code of 4-bit modulo-9 counter in
ModelSim, and capture the screenshot
of your simulated waveform.
Assume clock period Tclk=100ns, initially, the counter is reset
to Q3Q2Q1Q0=0000 you
need to simulate a complete counting cycle plus one more additional
clock period after it is reset to “0000” state.