In: Electrical Engineering
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer is
Port (
din:in STD_LOGIC_VECTOR (7 downto 0);
sel:in STD_LOGIC_VECTOR (2 downto 0);
dout : out STD_LOGIC);
end multiplexer;
architecture Behavioral of multiplexer is
begin
process (din,sel)
begin
case sel is
when
"000"=> dout <= din(7);
when
"001"=> dout <= din(6);
when
"010"=> dout <= din(5);
when
"011"=> dout <= din(4);
when
"100"=> dout <= din(3);
when
"101"=> dout <= din(2);
when
"110"=> dout <= din(1);
when
"111"=> dout <= din(0);
when
others=> dout <= din(0);
end case;
end process;
end Behavioral;
TEST BENCH:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_multiplexer_vhd IS
END tb_multiplexer_vhd;
ARCHITECTURE behavior OF tb_multiplexer_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplexer
PORT(
din :IN std_logic_vector(7 downto 0);
sel:IN std_logic_vector(2 downto 0);
dout :OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL din : std_logic_vector(7 downto 0) :=
(others=>'0');
SIGNAL sel : std_logic_vector(2 downto 0) :=
(others=>'0');
--Outputs
SIGNAL dout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplexer PORT MAP(din => din,
sel => sel,
dout => dout
);
process
din<= "10100011"; wait for 10ns;
sel<= "000"; wait for 10ns,
sel<= "001"; wait for 10ns,
sel<= "010"; wait for 10ns,
sel<= "011"; wait for 10ns,
sel<= "100"; wait for 10ns,
sel<= "101"; wait for 10ns,
sel<= "110"; wait for 10ns,
sel<= "111"; wait for 10ns,
wait;
end process
END;