Question

Write a VHDL code for a 8x8 bit multiplier. use structural approach. write the design code and testbench. Use for-generate if possible

Answer 1

VHDL: Multiplier
library ieee;
use ieee.std_logic_1164.all;
--library synplify; -- required for synthesis
--use synplify.attributes.all; -- required for synthesis
entity Multiplier is
port (
A_in : in std_logic_vector(7 downto 0 );
B_in : in std_logic_vector(7 downto 0 );
clk : in std_logic;
reset : in std_logic;
START : in std_logic;
RC : out std_logic_vector(15 downto 0 );
STOP : out std_logic);
end Multiplier;
use work.all;
architecture rtl of Multiplier is
signal ADD_cmd : std_logic;
signal Add_out : std_logic_vector(7 downto 0 );
signal C_out : std_logic;
signal LOAD_cmd : std_logic;
signal LSB : std_logic;
signal RA : std_logic_vector(7 downto 0 );
signal RB : std_logic_vector(7 downto 0 );
signal SHIFT_cmd : std_logic;
component RCA
port (
RA : in std_logic_vector(7 downto 0 );
RB : in std_logic_vector(7 downto 0 );
C_out : out std_logic;
Add_out : out std_logic_vector(7 downto 0 )
);
end component;
component Controller
port (
reset : in std_logic;
clk : in std_logic;
START : in std_logic;
LSB : in std_logic;
ADD_cmd : out std_logic;
SHIFT_cmd : out std_logic;
LOAD_cmd : out std_logic;
STOP : out std_logic
);
end component;
component Multiplicand
port (
reset : in std_logic;
A_in : in std_logic_vector(7 downto 0 );
LOAD_cmd : in std_logic;
RA : out std_logic_vector(7 downto 0 )
);
end component;
component Multiplier_Result
port (
reset : in std_logic;
clk : in std_logic;
B_in : in std_logic_vector(7 downto 0 );
LOAD_cmd : in std_logic;
SHIFT_cmd : in std_logic;
ADD_cmd : in std_logic;
Add_out : in std_logic_vector(7 downto 0 );
C_out : in std_logic;
RC : out std_logic_vector(15 downto 0 );
LSB : out std_logic;
RB : out std_logic_vector(7 downto 0 )
);
end component;
begin
inst_RCA: RCA
port map (
RA => RA(7 downto 0),
RB => RB(7 downto 0),
C_out => C_out,
Add_out => Add_out(7 downto 0)
);
inst_Controller: Controller
port map (
reset => reset,
clk => clk,
START => START,
LSB => LSB,
ADD_cmd => ADD_cmd,
SHIFT_cmd => SHIFT_cmd,
LOAD_cmd => LOAD_cmd,
STOP => STOP
);
inst_Multiplicand: Multiplicand
port map (
reset => reset,
A_in => A_in(7 downto 0),
LOAD_cmd => LOAD_cmd,
RA => RA(7 downto 0)
);
inst_Multiplier_Result: Multiplier_Result
port map (
reset => reset,
clk => clk,
B_in => B_in(7 downto 0),
LOAD_cmd => LOAD_cmd,
SHIFT_cmd => SHIFT_cmd,
ADD_cmd => ADD_cmd,
Add_out => Add_out(7 downto 0),
C_out => C_out,
RC => RC(15 downto 0),
LSB => LSB,
RB => RB(7 downto 0)
);
end rtl;

VHDL: TestBench

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all; --required for file I/O
use ieee.std_logic_textio.all; --required for file I/O
entity TESTBENCH is
end TESTBENCH;
architecture BEHAVIORAL of TESTBENCH is
component Multiplier
port (
A_in : in std_logic_vector(7 downto 0 );
B_in : in std_logic_vector(7 downto 0 );
clk : in std_logic;
RC : out std_logic_vector(15 downto 0 );
reset : in std_logic;
START : in std_logic;
STOP : out std_logic
);
end component;
signal A_in_TB, B_in_TB : std_logic_vector(7 downto 0 );
signal clk_TB, reset_TB, START_TB : std_logic;
signal STOP_TB : std_logic;
signal RC_TB: std_logic_vector(15 downto 0);
begin
-- instantiate the Device Under Test
inst_DUT : Multiplier
port map (
A_in => A_in_TB,
B_in => B_in_TB,
clk => clk_TB,
reset => reset_TB,
RC => RC_TB,
START => START_TB,
STOP => STOP_TB);
-- Generate clock stimulus
STIMULUS_CLK : process
begin
clk_TB <= '0';
wait for 10 ns;
clk_TB <= '1';
wait for 10 ns;
end process STIMULUS_CLK;
-- Generate reset stimulus
STIMULUS_RST : process
begin
reset_TB <= '0';
wait for 50 ns;
reset_TB <= '1';
wait;
end process STIMULUS_RST;
-- Generate multiplication requests
STIMULUS_START : process
file logFile : text is out "bus_log.txt"; -- set output file name
variable L: line;
variable A_temp, B_temp, i : integer;
begin
write(L, string'("A B Result")); -- include heading in file
writeline(logFile,L);
A_temp := 0; -- start A at 0
B_temp := 255; -- start B at 255
i := 1;
for i in 1 to 256 loop
A_in_TB <= STD_LOGIC_VECTOR(to_unsigned(A_temp,8));
B_in_TB <= STD_LOGIC_VECTOR(to_unsigned(B_temp,8));
START_TB <= '0';
wait for 100 ns;
START_TB <= '1'; -- request the multiplier to start
wait for 100 ns;
START_TB <= '0';
wait until STOP_TB = '1'; -- wait for the multiplier to finish
hwrite(L, A_in_TB); -- insert hex value of A in file
write(L, string'(" "));
hwrite(L, B_in_TB); -- insert hex value of B in file
write(L, string'(" "));
hwrite(L, RC_TB); -- insert hex value of result in file
writeline(logFile,L);
A_temp := A_temp + 1; -- increment value of A (Multiplicand)
B_temp := B_temp - 1; -- decrement value of B (Multiplier)
end loop;
wait;
end process STIMULUS_START;
end BEHAVIORAL;