Question

Provide the VHDL code and simulation results for a mod-7 counter, with asynchronous active low reset.

Answer 1

Design

module modN_ctr  
  # (parameter N = 7,  
     parameter WIDTH = 4)  
  
  ( input   clk,  
    input   rstn,  
    output  reg[WIDTH-1:0] out);  
  
  always @ (posedge clk) begin  
    if (!rstn) begin  
      out <= 0;  
    end else begin  
      if (out == N-1)  
        out <= 0;  
      else  
        out <= out + 1;  
    end  
  end  
endmodule 

Testbench

    module tb;  
      parameter N = 7;  
      parameter WIDTH = 4;  
      
      reg clk;  
      reg rstn;  
      wire [WIDTH-1:0] out;  
      
      modN_ctr u0  (    .clk(clk),  
                        .rstn(rstn),  
                        .out(out));  
      
      always #10 clk = ~clk;  
      
      initial begin  
        {clk, rstn} <= 0;  
      
        $monitor ("T=%0t rstn=%0b out=0x%0h", $time, rstn, out);  
        repeat(2) @ (posedge clk);  
        rstn <= 1;  
      
        repeat(20) @ (posedge clk);  
        $finish;  
      end  
    endmodule  

Simulation Result

ncsim> run
T=0 rstn=0 out=0xx
T=10 rstn=0 out=0x0
T=30 rstn=1 out=0x0
T=50 rstn=1 out=0x1
T=70 rstn=1 out=0x2
T=90 rstn=1 out=0x3
T=110 rstn=1 out=0x4
T=130 rstn=1 out=0x5
T=150 rstn=1 out=0x6
T=170 rstn=1 out=0x7
T=190 rstn=1 out=0x0
T=210 rstn=1 out=0x1
T=230 rstn=1 out=0x2
T=250 rstn=1 out=0x3
T=270 rstn=1 out=0x4
T=290 rstn=1 out=0x5
T=310 rstn=1 out=0x6
T=330 rstn=1 out=0x7
T=350 rstn=1 out=0x0
T=370 rstn=1 out=0x1
T=390 rstn=1 out=0x2
T=410 rstn=1 out=0x3
Simulation complete via $finish(1) at time 430 NS + 0

Please comment if anything else is needed