Write a VHDL code to use two ultrasonic sensors as detectors, placed one at entrance and...

Write a VHDL code to use two ultrasonic sensors as detectors, placed one at entrance and other at exit of a parking space. When the ultrasonic detects a car, use a counter to count the cars entering and decrement when a car exits. There is an RGB led place at each gate (entry &exit) which is used to indicate opening and closing of gates. Entry gate LED turns green when car detected and space available. LED stays red when no car detected, or car detected but no space available. Exit LED stays red but turns green when car detected by ultrasonic.

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Manojponduru answered 2 years ago

Write a VHDL code for a 8x8 bit multiplier. use structural approach. write the design code...

Write a VHDL code for a 8x8 bit multiplier. use structural approach. write the design code and testbench. Use for-generate if possible

Write VHDL code (behavior model) to implement a 4-bit modulo-9 counter and simulate your VHDL code...

Write VHDL code (behavior model) to implement a 4-bit modulo-9 counter and simulate your VHDL code of 4-bit modulo-9 counter in ModelSim, and capture the screenshot of your simulated waveform. Assume clock period Tclk=100ns, initially, the counter is reset to Q3Q2Q1Q0=0000 you need to simulate a complete counting cycle plus one more additional clock period after it is reset to “0000” state.

Write VHDL code for the following: Use HEX-to-seven segment display converters to display the inputs and...

Write VHDL code for the following: Use HEX-to-seven segment display converters to display the inputs and results for a 4-bit adder. The inputs are unsigned 4-bit binary numbers. The outcome is a 4-bit binary adder with LED display. First you need to create a symbol for the HEX-to-seven segment display converter. Then implement a 4-bit adder using VHDL. Finally, connect three HEX-to-seven segment display converters to display input X, input Y, and sum S.

4. Use generate statement to write VHDL code for a 16 bit adder assuming the only...

4. Use generate statement to write VHDL code for a 16 bit adder assuming the only available building block is a full adder. Thank

a) i) The following VHDL code contains erroneous syntax. Re write the code in its corrected...

a) i) The following VHDL code contains erroneous syntax. Re write the code in its corrected format onto your answer sheet. You may assume that din is a 16-bit vector and that the ld, lr and cl inputs are 1-bit wide. lp: process(clk) signal reg : std_logic_vector(15 downt begin if cl=’1’ then reg := (others:=’0’); else if clk=’1’ and clkevent then if ld=’1’ reg <= din; end if; if lr=’1’ then reg := reg(14 downto 0) & “0 else reg...

Write a VHDL code for a 4-bit comparator which takes two 4-bit input values and (0.5)...

Write a VHDL code for a 4-bit comparator which takes two 4-bit input values and (0.5) determines whether the numbers are equal. 2. 2. Write a structural VHDL code to implement the circuit of Fig. 2, using the components (0.5) developed in 1.3 and 2.1. 2. 3. Write a VHDL test bench for the above and verify by simulation. (0.5) 2. 4. Implement the design in an FPGA (Note: You may need a `clock manager' to reduce (1.0) the clock...

I am trying to write the code for an 8 bit adder in VHDL so that...

I am trying to write the code for an 8 bit adder in VHDL so that I can program it onto my Elbert V2 Spartan 3A FPGA Development Board, but I keep getting errors. Any ideas what I am doing wrong? library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity adder8bit is Port ( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); cin : in STD_LOGIC; o : out STD_LOGIC_VECTOR(7 downto 0); cout : out STD_LOGIC); end adder8bit; architecture Behavioral...

Write a VHDL code to implement a Finite State Machine that with an 8 bit sequence...

Write a VHDL code to implement a Finite State Machine that with an 8 bit sequence input (can be any sequence, but lets say it is 11001000), determine how many states there are as well; so if the input sequence is correct it will show the number 1 in a 7 segment display, otherwise it will be 0 in the same 7 segment display. If the input sequence is incorrect, start from the beginning.

write the vhdl code to get the moore and mealy machine to detect the sequence 1101...

write the vhdl code to get the moore and mealy machine to detect the sequence 1101 (in c++)

How do you write a VHDL code for this The SecondGenerator block generates the second count...

How do you write a VHDL code for this The SecondGenerator block generates the second count i.e; it increments an internal variable once every second from 0 to 59 and then rolls back to 0. That (std_logic_vector) variable can be assigned to a (std_logic_vector) signal second[5..0] which comes out of the block. Note that this is a 6-bit std_logic_vector value because counts up to 59 can be accommodated in 6 binary digits (26 = 64). As most clocks do not...

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