Question

Write a VHDL code for a 4-bit comparator which takes two 4-bit input values and (0.5) determines whether the numbers are equal. 2. 2. Write a structural VHDL code to implement the circuit of Fig. 2, using the components (0.5) developed in 1.3 and 2.1. 2. 3. Write a VHDL test bench for the above and verify by simulation. (0.5) 2. 4. Implement the design in an FPGA (Note: You may need a `clock manager' to reduce (1.0) the clock frequency).

Answer 1

Vhdl code for the comparing two 4 bit values is

library IEEE;

use IEEE.std_logic_1164.all;

entity compare is

port ( inp1 :in std_logic_vector(3 downto 0);

inp2 :in std_logic_vector(3 downto 0);

output :out std_logic);

end compare;

architecture comp of compare is

signal s : std_logic_vector(3 downto 0);

begin

s <= not ( inp1 xor inp2);

output <= s(0) and s(1) and s(2) and s(3);

end comp;

VHDL TESTBENCH FOR THE ABOVE VHDL IS

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

-- entity declaration for your testbench.

--Notice that the entity port list is empty here.

entity tb_compare is

end tb_compare;

architecture behavior of tb_compare is

-- component declaration for the unit under test (uut)

component compare is

port ( inp1 :in std_logic_vector(3 downto 0);

inp2 :in std_logic_vector(3 downto 0);

output :out std_logic);

end component;

--declare inputs and initialize them to zero.

signal inp1 : std_logic_vector(3 downto 0) := "0000";

signal inp2 : std_logic_vector(3 downto 0) := "0000";

--declare outputs

signal output : std_logic;

begin

uut : compare port map (

inp1 => inp1,

inp2 => inp2,

output => output

);   

  

inp1 <= "0001" after 5 ns,

"0010" after 10 ns,

"0000" after 25 ns;

end;

The simulation wave form is

when they are equal the output would be 1 else zero