Question

Write VHDL code for the following:

Use HEX-to-seven segment display converters to display the inputs and results for a 4-bit adder. The inputs are unsigned 4-bit binary numbers. The outcome is a 4-bit binary adder with LED display.

First you need to create a symbol for the HEX-to-seven segment display converter. Then implement a 4-bit adder using VHDL. Finally, connect three HEX-to-seven segment display converters to display input X, input Y, and sum S.

Answer 1

-- design file

library ieee;
use ieee.std_logic_1164.all;

entity seven_segment is
port (
   hex_in : in std_logic_vector(3 downto 0);
   hex_out : out std_logic_vector (6 downto 0)
);
end seven_segment;

architecture behave of seven_segment is
--signal temp1 : std_logic_vector(6 downto 0);
begin

   hex_out <= "1111110" when hex_in = "0000" else
              "0110000" when hex_in = "0001" else
              "1101101" when hex_in = "0010" else
              "1111001" when hex_in = "0011" else
              "0110011" when hex_in = "0100" else
              "1011011" when hex_in = "0101" else
              "1011111" when hex_in = "0110" else
              "1110000" when hex_in = "0111" else
              "1111111" when hex_in = "1000" else
              "1111011" when hex_in = "1001" else
              "1111110" ;
    
end behave;

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
port (
   A    : in std_logic;
   B    : in std_logic;
   Cin : in std_logic;
   Sum : out std_logic;
   Cout : out std_logic
);
end fulladder;

architecture behave_fa of fulladder is
begin
   Sum <= (A xor B xor Cin);
   Cout <= (A and B) or (A and Cin) or (B and Cin);
end behave_fa;

library ieee;
use ieee.std_logic_1164.all;

entity fulladder_4bit is
port (
   A    : in std_logic_vector(3 downto 0);
   B    : in std_logic_vector(3 downto 0);
   Cin : in std_logic;
   Sum : out std_logic_vector(3 downto 0);
   Cout : out std_logic
);
end fulladder_4bit;

architecture behave_fa_4bit of fulladder_4bit is
component fulladder
port (
   A    : in std_logic_vector (3 downto 0);
   B    : in std_logic_vector (3 downto 0);
   Cin : in std_logic;
   Sum : out std_logic_vector (3 downto 0);
   Cout : out std_logic
);
end component;

signal temp : std_logic_vector(3 downto 0);
begin
U0 : fulladder port map (A(0), B(0), Cin    , Sum(0), temp(0));
U1 : fulladder port map (A(1), B(1), temp(0), Sum(1), temp(1));
U2 : fulladder port map (A(2), B(2), temp(1), Sum(2), temp(2));
U3 : fulladder port map (A(3), B(3), temp(2), Sum(3), temp(3));
Cout <= temp(3);
end behave_fa_4bit;

library ieee;
use ieee.std_logic_1164.all;

entity top_level is
port (
A    : in std_logic_vector (3 downto 0);
B    : in std_logic_vector (3 downto 0);
Cin : in std_logic;
Sum : in std_logic_vector (3 downto 0);
Out1, Out2, Out3 : out std_logic_vector (6 downto 0)
);

architecture behave_top of top_level is
component fulladder_4bit is
port (
   A    : in std_logic_vector (3 downto 0);
   B    : in std_logic_vector (3 downto 0);
   Cin : in std_logic;
   Cout : out std_logic
);
end component;

component seven_segment is
port (
   hex_in : in std_logic_vector (3 downto 0);
   hex_out : out std_logic_vector (6 downto 0)
);
end component;
signal Sum : std_logic_vector (3 downto 0);
signal Cout : std_logic;
begin

DUT1 : fulladder_4bit (A => A, B => B, Cin => Cin, Sum => Sum, Cout => Cout);
DUT2 : seven_segment (hex_in => A, hex_out => Out1);
DUT3 : seven_segment (hex_in => B, hex_out => Out2);
DUT4 : seven_segment (hex_in => Sum, hex_out => Out3);

end behave_top;