Question

Write VHDL code (behavior model) to implement a 4-bit modulo-9 counter and simulate your VHDL code of 4-bit modulo-9 counter in ModelSim, and capture the screenshot

of your simulated waveform.

Assume clock period Tclk=100ns, initially, the counter is reset to Q₃Q₂Q₁Q₀=0000 you need to simulate a complete counting cycle plus one more additional clock period after it is reset to “0000” state.

Answer 1

--VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mod9_counter is
   port (   clock   : in std_logic;
       reset   : in std_logic;
       Q3   : out std_logic;
       Q2   : out std_logic;
       Q1   : out std_logic;
       Q0   : out std_logic
   );
end mod9_counter;

architecture arch of mod9_counter is

signal count : std_logic_vector(3 downto 0):= "0000";

begin

process (clock, reset)
begin
   if (reset = '1') then
       count <= "0000";
   else
       if (clock'event and clock = '1') then
           if (count = "1000") then
               count <= "0000";
           else
               count <= count + "0001";
           end if;
       end if;
   end if;
end process;

Q3   <= count(3);
Q2   <= count(2);
Q1   <= count(1);
Q0   <= count(0);

end arch;

---------------------------------------------------------------------------------------------------------------------------------------------------------------------

--Testbench

library IEEE;
use IEEE.Std_logic_1164.all;

entity mod9_counter_tb is
end;

architecture bench of mod9_counter_tb is

component mod9_counter
   port (   clock   : in std_logic;
       reset   : in std_logic;
       Q3   : out std_logic;
       Q2   : out std_logic;
       Q1   : out std_logic;
       Q0   : out std_logic
   );
end component;

signal clock: std_logic;
signal reset: std_logic;
signal Q3: std_logic;
signal Q2: std_logic;
signal Q1: std_logic;
signal Q0: std_logic ;

constant clock_period: time := 100 ns;
signal stop_the_clock: boolean;

begin

uut: mod9_counter port map ( clock => clock,
reset => reset,
Q3 => Q3,
Q2 => Q2,
Q1 => Q1,
Q0 => Q0 );

stimulus: process
begin
  
   reset <= '0';
   wait for 12 * clock_period;

   reset <= '1';
   wait for clock_period;

   reset <= '0';
   stop_the_clock <= true;
  
wait;
end process;

clocking: process
begin
while not stop_the_clock loop
clock <= '0', '1' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;

end;

---------------------------------------------------------------------------------------------------------------------------------------------------------------------

--Simulation