Question

I am trying to write the code for an 8 bit adder in VHDL so that I can program it onto my Elbert V2 Spartan 3A FPGA Development Board, but I keep getting errors. Any ideas what I am doing wrong?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder8bit is
Port ( a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
cin : in STD_LOGIC;
o : out STD_LOGIC_VECTOR(7 downto 0);
cout : out STD_LOGIC);
end adder8bit;

architecture Behavioral of adder8bit is

component fulladder is
   Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
o : out STD_LOGIC;
cout : out STD_LOGIC
);
end component;

signal c : STD_LOGIC_VECTOR(6 downto 0);

begin

PROCESS (a,b,cin)
BEGIN

o(0) <= a(0) xor b(0) xor cin;
c(0) <= (cin and b(0)) or (cin and a(0)) or (a(0) and b(0));

for i in 1 to 7 loop

o(i) <= a(i) xor b(i) xor c(i-1);
c(i) <= (c(i-1) and b(i)) or (c(i-1) and a(i)) or (a(i) and b(i));

end loop;

cout <= c(6);

END PROCESS;

end Behavioral;

Answer 1

the corrected code is:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder8bit is
Port (    a : in STD_LOGIC_VECTOR(7 downto 0);
           b : in STD_LOGIC_VECTOR(7 downto 0);
           cin : in STD_LOGIC;
           o : out STD_LOGIC_VECTOR(7 downto 0);
           cout : out STD_LOGIC);
end adder8bit;

architecture Behavioral of adder8bit is

signal c : STD_LOGIC_VECTOR(8 downto 0);

begin

PROCESS (a,b,cin,c)
BEGIN

c(0)<=cin;
for i in 0 to 7 loop

o(i) <= a(i) xor b(i) xor c(i);
c(i+1) <= (c(i) and b(i)) or (c(i) and a(i)) or (a(i) and b(i));

end loop;

cout <= c(8);

END PROCESS;

end Behavioral;

Note:

1. Here, you are not using structural model, hence no need to take the component instanstiation.

2. In order to properly execute the program remove the lines

o(0) <= a(0) xor b(0) xor cin;
c(0) <= (cin and b(0)) or (cin and a(0)) or (a(0) and b(0));

add them also in for loop as i did. assign C(0) intially to cin. and take c as 9 bit data.

3. Assign c(8) to cout.

4. another important point inclue signal c in the process.