In: Electrical Engineering
How do you write a VHDL code for this
The SecondGenerator block generates the second count i.e; it increments an internal variable once every second from 0 to 59 and then rolls back to 0. That (std_logic_vector) variable can be assigned to a (std_logic_vector) signal second[5..0] which comes out of the block. Note that this is a 6-bit std_logic_vector value because counts up to 59 can be accommodated in 6 binary digits (26 = 64). As most clocks do not display second counts so this value is not utilized any further here. This block also generates a pulse every time the second counter rolls over i.e. every 1 minute. This comes out as the std_logic signal minute_out .
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity digi_clk is
port (clk1 : in std_logic;--counting pulses
seconds : out
std_logic_vector(5 downto 0);--second key output
);
end digi_clk;
architecture Behavioral of digi_clk is
signal sec : integer range 0 to 60 :=0;
signal count : integer :=1;
signal clk : std_logic :='0';
signal minute_out : std_logic;
begin
seconds <= conv_std_logic_vector(sec,6);
--clk generation.For 100 MHz clock this generates 1 Hz clock.
process(clk1)
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 50000000) then
clk <= not clk;
count <=1;
end if;
end if;
end process;
process(clk) --period of clk is 1 second.
begin
if(clk'event and clk='1') then
sec <= sec+ 1;
if(sec = 59) then --after 59 it should be reset
begin
sec<=0; --for rolling the timer continuously
minute_out <= ‘1’;--One minute count
end
end if;
end if;
end process;
end Behavioral;