Question

a) i) The following VHDL code contains erroneous syntax. Re write the code in its corrected format onto your answer sheet. You may assume that din is a 16-bit vector and that the ld, lr and cl inputs are 1-bit wide.

lp: process(clk)
signal reg : std_logic_vector(15 downt
begin
if cl=’1’ then
reg := (others:=’0’);
else
if clk=’1’ and clkevent then
if ld=’1’
reg <= din;
end if;
if lr=’1’ then
reg := reg(14 downto 0) & “0
else
reg := ‘0’ && reg(15 downto
end if;
end if;
end process

Describe, in your own words, the functionality of the circuit
described by the corrected VHDL code from i). Your answer
must explain the purpose of the lr, ld and cl inputs.

Answer 1

The circuit is a 16 bit shift register with preload and asynchronous clear.

The cl input clears the register. The ld input loads the register with data from din. The lr input decides the direction of the shift, 0 for right shift and 1 for left shift.

Design:

library ieee;
use ieee.std_logic_1164.all;

entity shift is
port (
    clk : in std_logic;
    cl   : in std_logic;
    ld   : in std_logic;
    lr   : in std_logic;
    din : in std_logic_vector(15 downto 0);
    dout : out std_logic_vector(15 downto 0)
);
end shift;

architecture arch of shift is begin

lp : process (clk)
    variable reg : std_logic_vector(15 downto 0);
begin
    if (cl = '1') then
      reg := (others => '0');
    else
      if (clk'event and clk = '1') then
        if (ld = '1') then
          reg := din;
        else
          if (lr = '1') then
            reg := reg(14 downto 0) & "0";
          else
            reg := "0" & reg(15 downto 1);
          end if;
        end if;
      end if;
    end if;
    dout <= reg;
end process;
end arch;

Testbench:

library ieee;
use ieee.std_logic_1164.all;

entity tb_shift is
end tb_shift;

architecture tb of tb_shift is

    component shift
        port (clk : in std_logic;
              cl   : in std_logic;
              ld   : in std_logic;
              lr   : in std_logic;
              din : in std_logic_vector(15 downto 0);
              dout : out std_logic_vector(15 downto 0));
    end component;

    signal clk : std_logic;
    signal cl   : std_logic;
    signal ld   : std_logic;
    signal lr   : std_logic;
    signal din : std_logic_vector(15 downto 0);
    signal dout : std_logic_vector(15 downto 0);

    constant TbPeriod : time := 1000 ns;
    signal TbClock : std_logic := '0';
    signal TbSimEnded : std_logic := '0';

begin

    dut : shift
    port map (clk => clk,
              cl   => cl,
              ld   => ld,
              lr   => lr,
              din => din,
              dout => dout);

    -- Clock generation
    TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';

    clk <= TbClock;

    stimuli : process
    begin
        cl <= '0';
        ld <= '0';
        lr <= '0';
        din <= "0000000000000000";

        -- Reset generation
        cl <= '1';
        wait for 100 ns;
        cl <= '0';
        wait for 100 ns;

        ld <= '1';
        din <= "1111111111111111";
        wait for 2 * TbPeriod;
      
        ld <= '0';
        lr <= '0';
        din <= "0000000000000000";
        wait for 5 * TbPeriod;

        lr <= '1';
        din <= "0000000000000000";
        wait for 5 * TbPeriod;

        -- Stop the clock and hence terminate the simulation
        TbSimEnded <= '1';
        wait;
    end process;

end tb;