Question

Write a VHDL code to implement a Finite State Machine that with an 8 bit sequence input (can be any sequence, but lets say it is 11001000), determine how many states there are as well; so if the input sequence is correct it will show the number 1 in a 7 segment display, otherwise it will be 0 in the same 7 segment display. If the input sequence is incorrect, start from the beginning.

Answer 1

The first step in writing the VHDL for this FSM is to define the VHDL entity. The VHDL entity describes the external interface of the system you are designing which includes the inputs, the outputs, and the name of the entity. The general form of an entity looks like this:

ENTITY -entityName- is

PORT (-portName1- : -signalDirection- -type-;
    -portName2- : -signalDirection- -type-;
    ---
    -portName_n- : -signalDirection- -type-;
END -entityName-;

--Note: user defined entries are between the dashes

Using this template, the entity for the simple FSM can be created. The name of the entity will be SimpleFSM, the inputs are a clock signal, the reset signal and the P signal, and the output is the R signal. It should be mentioned that the clock signal is the periodic high-low signal that controls the timing to this synchronous system. Any synchronous system has one controlling clock signal that synchronizes all of the blocks in the system making them change at the same time.

Putting all of the information together gives a SimpleFSM entity that looks like this:

ENTITY SimpleFSM is
PORT (clock:    IN STD_LOGIC;
      P:        IN STD_LOGIC;
      reset:    IN STD_LOGIC;
      R :       OUT STD_LOGIC);
END SimpleFSM;

One final note about the entity is that all the inputs and outputs are single bits and so can use the data type std_logic which is the standard type in VHDL for single bit signals.

The next step is to define the functionality of the entity; this block of VHDL is called the architecture. The functionality that we are implementing is that of the state machine defined in figure 1. The example below shows the code that would be needed to implement the SimpleFSM. While this code is specific to the SimpleFSM, I will describe what each of the sections of the code do so that it will be an easy process to replace this code with code for your own state machine.

-- Architecture definition for the SimpleFSM entity
Architecture RTL of SimpleFSM is
TYPE State_type IS (A, B, C, D);  -- Define the states
        SIGNAL State : State_Type;    -- Create a signal that uses 
                                                              -- the different states
BEGIN 
  PROCESS (clock, reset) 
  BEGIN 
    If (reset = ‘1’) THEN            -- Upon reset, set the state to A
        State <= A;
 
    ELSIF rising_edge(clock) THEN    -- if there is a rising edge of the
                         -- clock, then do the stuff below
 
        -- The CASE statement checks the value of the State variable,
        -- and based on the value and any other control signals, changes
        -- to a new state.
        CASE State IS
 
                -- If the current state is A and P is set to 1, then the
                -- next state is B
                WHEN A => 
                        IF P='1' THEN 
                                State <= B; 
                        END IF; 
 
                -- If the current state is B and P is set to 1, then the
                -- next state is C
                WHEN B => 
                        IF P='1' THEN 
                                State <= C; 
                        END IF; 
 
                -- If the current state is C and P is set to 1, then the
                -- next state is D
                WHEN C => 
                        IF P='1' THEN 
                                State <= D; 
                        END IF; 
 
                -- If the current state is D and P is set to 1, then the
                -- next state is B.
                -- If the current state is D and P is set to 0, then the
                -- next state is A.
                WHEN D=> 
                        IF P='1' THEN 
                                State <= B; 
                        ELSE 
                                State <= A; 
                        END IF; 
                WHEN others =>
                        State <= A;
        END CASE; 
    END IF; 
  END PROCESS;

-- Decode the current state to create the output
-- if the current state is D, R is 1 otherwise R is 0
R <= ‘1’ WHEN State=D ELSE ‘0’;
END rtl;

That is the entirety of the code needed for the state machine. Now let’s look at some of the details of the architecture code.

The architecture definition states:

Architecture RTL of SimpleFSM is

This statement is a standard one for a VHDL architecture and it basically states the level of abstraction that will be described in the architecture. RTL, which stands for register-transfer level, is a mid-level of abstraction.

Behavioural is the highest level of abstraction and when writing behavioural code you simply need to define the relationships between inputs and outputs without specifying anything about how those relationships will be implemented. Sometimes behavioural descriptions are too high level and cannot actually be synthesized into hardware. If you are doing a simulation and just need a block to behave in a certain way, then a behavioural model will be adequate.

Structural code is the lowest level of abstraction. When writing structural code, you describe how the low level structures (e.g., logic gates) connect together to give the system that you want. If you need precise control over the logic gates that will be created, a structural model is what you need.

RTL fits in the middle. It specifically describes the relationships between inputs and outputs be describing how data moves between registers in the hardware. RTL descriptions are implementable in hardware. For this particular example, it is not very important to understand the nuances of the architecture type (behavioural, RTL, or structural), you just need to define it as something.

The next block defines the states and creates a signal that will have a defined state as its value. There should be a one-to-one mapping of the states listed here to the states represented by the circles in the FSM diagram.

TYPE State_type IS (A, B, C, D); -- the 4 different states
        SIGNAL State : State_Type;   -- Create a signal that uses 
                                 -- the 4 different states

The next statement is the start of a VHDL process with the signals clock and reset in its sensitivity list

PROCESS (clock, reset) 
  BEGIN 
    If (reset = ‘1’) THEN   -- Upon reset, set the state to A
      State <= A;
 
    ELSIF rising_edge(clock) THEN

Again, there are many details about process declarations that can be ignored for this article. All that you need to understand is that in RTL level design, this process will create a register for all of the signals that have assignments to them within the process. In this case only the State signal has an assignment, so a register made up of enough flip flops to represent the value of State will be created. This register will be synchronized to the rising edge of clock and will be asynchronously resettable by the reset signal. A general visual representation of the circuit that will be created by the process can be seen back in figure 2.

The body of the code following the rising_edge(clock) statement is a VHDL case statement that will be synthesized into the logic for controlling what value State changes to on each rising edge of clock. For example, the statement

  WHEN A => 
    IF P='1' THEN 
      State <= B; 
    END IF;

means that if State has the value of A, then if the signal P is 1, change State to B on the rising clock edge.

The last statement in the case is

  WHEN others =>
    State <= A;

This statement is a catch-all statement to make sure that if State somehow had a value not equal to A, B, C, or D, then it would reset to a value of A.

The final section of code is done outside the process and creates a block of combinational logic.

  R <= ‘1’ WHEN State=D ELSE ‘0’;

What this statement is doing is determining the value of the output R. R will be a 1 if the State is D and it will be a 0 in all other states. One thing of note here is that the output of this state machine is dependent only on the state. State machines where the present state is the only thing determining the output are called Moore State Machines. The other broad category of state machines is one where the output depends not only on the current state, but also on the inputs. This type of state machine is called a Mealy State Machine. In practice, it generally does not matter what kind of state machine you use, it doesn’t even matter if you know what kind of state machine you are using. All that matters is that you implement the state machine as you have defined it.

The last few steps in designing this system would involve simulating the system to make sure it does what it is expected to do and then finally synthesizing the hardware for implementation on a physical system (CPLD, FPGA, ASIC etc.)

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module fsm01(clk,reset,one,zero,out);
  parameter STATE_0_0 = 0;     // 0 zeroes, 0 ones
  parameter STATE_0_1 = 1;     // 1 zero, 0 ones
  parameter STATE_0_2 = 2;     // 2 zeroes, 0 ones
  parameter STATE_1_0 = 3;     // 0 zeroes, 1 one
  parameter STATE_1_1 = 4;     // 1 zero, 1 one
  parameter STATE_1_2 = 5;     // 2 zeroes, 1 one
  parameter STATE_2_0 = 6;     // 0 zeroes, 2 ones
  parameter STATE_2_1 = 7;     // 1 zero, 2 ones
  parameter STATE_2_2 = 8;     // 2 zeroes, 2 ones

  input clk,reset,one,zero;
  output out;

  // level-to-pulse converters for ZERO and ONE inputs
  reg last_one,last_zero;
  wire input_one,input_zero;
  always @ (posedge clk)
  begin
    last_one <= reset ? 0 : one;
    last_zero <= reset ? 0 : zero;
  end
  assign input_one = ~last_one & one;
  assign input_zero = ~last_zero & zero;

  // fsm
  reg [3:0] state;
  always @ (posedge clk)
  begin
    if (reset) state <= STATE_0_0;
    else case (state)
     STATE_0_0: state <= input_one ? STATE_1_0 : input_zero ? STATE_0_1 : state;
     STATE_0_1: state <= input_one ? STATE_1_1 : input_zero ? STATE_0_2 : state;
     STATE_0_2: state <= input_one ? STATE_1_2 : state;
     STATE_1_0: state <= input_one ? STATE_2_0 : input_zero ? STATE_1_1 : state;
     STATE_1_1: state <= input_one ? STATE_2_1 : input_zero ? STATE_1_2 : state;
     STATE_1_2: state <= input_one ? STATE_2_2 : state;
     STATE_2_0: state <= input_zero ? STATE_2_1 : state;
     STATE_2_1: state <= input_zero ? STATE_2_2 : state;
     STATE_2_2: state <= state;
     default: state <= STATE_0_0;    // transition out of unused states
    endcase
  end

  // it's a Moore machine so output only depends on current state.
  // Note: OUT might glitch as the logic decodes the current state.
  assign out = (state == STATE_2_2);