Question

draw state machine and write verilog code of an ALU unit that shifts left when the control signal 'OP' is 00, shifts right when control is ''01'' and increments when control is ''10''. Fpr control ''11'' , it does nothing. inputs are Date [3:0] and clk, and the output is Out [3:0]

Answer 1

State diagram:

Verilog Code:

module ALU(input [3:0] Date, input [1:0] OP, output [3:0] Out);

assign Out=tmp(Date,OP);

function [3:0]tmp;

input [3:0]Date;

input [1:0]OP;

begin

case(OP)

2'b00: tmp = Date<<1;

2'b01: tmp = Date>>1;

2'b10: tmp = Date+1;

2'b10: ;

endcase

end

endfunction

endmodule

RTL Schematic:

Simulation:(Test bench)

`timescale 1ns / 1ps

module testalu;

// Inputs

reg [3:0] Date;

reg [1:0] OP;

// Outputs

wire [3:0] Out;

// Instantiate the Unit Under Test (UUT)

ALU uut (

.Date(Date),

.OP(OP),

.Out(Out)

);

initial begin

// Initialize Inputs

Date = 0;

OP = 0;

// Wait 100 ns for global reset to finish

#100;

Date = 1;

OP = 2'b00;

#100;

Date = 1;

OP = 2'b01;

#100;

Date = 1;

OP = 2'b10;

#100;

Date = 1;

OP = 2'b11;

#100;

  

// Add stimulus here

end

  

endmodule