Question

write an Arithmetic Logic Unit (ALU) in verilog.

Answer 1

An Arithmetic Logic Unit (ALU) performs Arithmetic operations on input numbers like Addition, Subtraction, Division, Multiplication, & digital Gates operations like AND, OR, NOT, or any other operation you want.

Here, we will be using sequential approach for designing ALU in verilog. We will input numbers from user and will apply “CASE” statement on operation. On the base of user choice, the required operation will be performed and result will be displayed to the user.

Verilog Code For Arithmetic Logic Unit (ALU)

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module ALU( A, B, Op, R ); input [7:0] A,B; input [2:0] Op; output [7:0] R; wire [7:0] Reg1,Reg2; reg [7:0] Reg3; assign Reg1 = A; assign Reg2 = B; assign R = Reg3; always @(Op or Reg1 or Reg2) begin case (Op) 0 : Reg3 = Reg1 + Reg2; //addition 1 : Reg3 = Reg1 - Reg2; //subtraction 2 : Reg3 = ~Reg1; //NOT gate 3 : Reg3 = ~(Reg1 & Reg2); //NAND gate 4 : Reg3 = ~(Reg1 | Reg2); //NOR gate 5 : Reg3 = Reg1 & Reg2; //AND gate 6 : Reg3 = Reg1 | Reg2; //OR gate 7 : Reg3 = Reg1 ^ Reg2; //XOR gate endcase end endmodule

Verilog Code Explanation

We have taken “R” as output & A,B as input. Since we are using sequential approach, we define register R3 of same dimension. Our program will execute if any of input or “Operation” will change. We have applied Case statement on “OP” so the proper operation will be selected through Case statements.

You can add as many operations as you want. The testbench for above code is given below. You can change test bench values or change time interval. This has been tested on Xilinx ISE.

TestBench For ALU

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`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// module tb_alu; // Inputs reg [7:0] A; reg [7:0] B; reg [2:0] Op; // Outputs wire [7:0] R; // Instantiate the Unit Under Test (UUT) ALU uut ( .A(A), .B(B), .Op(Op), .R(R) ); initial begin // Apply inputs. A = 8'b01101010; B = 8'b00111011; Op = 0; #100; Op = 1; #100; Op = 2; #100; Op = 3; #100; Op = 4; #100; Op = 5; #100; Op = 6; #100; Op = 7; #100; end endmodule