Question

The heart of a computer system is an ARITHMETIC AND LOGIC UNIT (ALU) which is responsible for executing arithmetic (e.g., addition, subtraction, etc.) and logic (e.g., AND, OR, etc.) operations. In this project, you will design, simulate, and implement a simple 1-bit ALU.

The truth table for ALU is given below:

Operation Selection Inputs Operation Output(s)
S0 S1 A B
0 0 A AND B AB
0 1 A NOR B (A+B)’
1 0 A XNOR B (A⊕B)’
1 1 A SUB B Borrow, Difference

Answer 1

Verilog code for the given design

// Code your design here

module ALU(A,B,s0,s1,Y,borrow_carry);

input A,B;

input s0,s1;

output reg Y;

output reg borrow_carry;

  

  

always @(*)

begin

case ({s1,s0})

00: begin Y= (A & B); borrow_carry = 1'b0;end

01: begin Y=(~(A | B)); borrow_carry = 1'b0;end

10: begin Y= (~(A ^ B)); borrow_carry = 1'b0; end

11: begin Y= (A ^ B); borrow_carry = ((~ A ) & B); end

default begin Y=1'b0; borrow_carry = 1'b0; end

endcase

end

endmodule

  

Test bench code

// Code your testbench here

// or browse Examples

module test;

reg A,B;

reg s0,s1;

wire Y;

wire borrow_carry;

  

ALU dut(A,B,s0,s1,Y,borrow_carry);

  

initial

begin

$dumpfile ("var.vcd");

$dumpvars ;

A=1'b1;B=1'b1;s1=1'b1;s0=1'b1;#10;

s1=1'b0;s0=1'b1;#10;

s1=1'b1;s0=1'b0;#10;

s1=1'b0;s0=1'b0;#10;

A=1'b1;B=1'b0;s1=1'b1;s0=1'b1;#10;

s1=1'b0;s0=1'b1;#10;

s1=1'b1;s0=1'b0;#10;

s1=1'b0;s0=1'b0;#10;

$finish;

end

endmodule

Simulation results