In: Electrical Engineering
How do I implement Image Processing using VHDL for FPGA? Please provide VHDL code
Image processing on FPGA using Verilog HDL:
Module for reading and processing image
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// Verilog project: Image processing in Verilog
`include "parameter.v" // Include definition file
module image_read #( parameter
WIDTH = 768, // Image width
HEIGHT = 512, // Image height
INFILE = "./img/your_image.hex", // image file
START_UP_DELAY = 100, //Delay during start up time
HSYNC_DELAY = 160, // Delay between
HSYNC pulses
VALUE= 100, // value for Brightness operation
THRESHOLD= 90,
// Threshold value for Threshold and contrast operation
ValueToMul=2,
ValueToAdd= 10,
// Value to add in contrast addition
ValueToSubtract= 15 ,
// Value to add in contrast addition
SIGN=1 // Sign value using for brightness operation
// SIGN = 0: Brightness subtraction
// SIGN = 1: Brightness addition
)
( input HCLK, // clock
input HRESETn, // Reset (active low)
output reg VSYNC, // Vertical synchronous pulse
// This signal is often a way to indicate that one entire image is transmitted.
// Just create and is not used, will be used once a video or many images are transmitted.
output reg HSYNC,
// Horizontal synchronous pulse
// An HSYNC indicates that one line of the image is transmitted.
//Used to be a horizontal synchronous signals for writing bmp file.
output reg [7:0] DATA_R0, // 8 bit Red data (even)
output reg [7:0] DATA_G0, // 8 bit Green data (even)
output reg [7:0] DATA_B0, // 8 bit Blue data (even)
output reg [7:0] DATA_R1, // 8 bit Red data (odd)
output reg [7:0] DATA_G1, // 8 bit Green data (odd)
output reg [7:0] DATA_B1, // 8 bit Blue data (odd)
output ctrl_done // Done flag
);
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//-------------------------------------------------//
// -------- Reading data from input file ----------//
//-------------------------------------------------//
initial begin
$readmemh(INFILE,total_memory,0,sizeOfLengthReal-1); // read file from INFILE
end
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