Question

use modelsim write Verilog code for the following digital logic circuits and then simulate them by writing a testbench module for each of them ,

(a)The FSMs for the snail problem that is in the slides (a snail crawls over a tape that has 0 and 1 and smiles if it has detected the '10' bits using both Moore and Mealy FSM. Note that the pattern is '10' not '01' as in the slides.

(b) A rock-paper-scissor game played by two users (A and B) to indicate who's won or draw then they input their choice. Hint: A's output is 1 if A has won, both A's and B's signals is 0 if it was a draw.

Answer 1

Verilog code:-

module morfsm(din, reset, clk, y);
output reg y;
input din;
input clk;
input reset;
reg [1:0] cst, nst;
parameter S0 = 2'b00,
          S1 = 2'b01,
          S2 = 2'b10,
always @(cst or din)
 begin
 case (cst)
   S0: if (din == 1'b1)
          begin
         nst = S1;
          y=1'b0;
          end
      else
          begin
          nst = cst;
          y=1'b0;
          end  
S1: if (din == 1'b0)
          begin
        nst = S2;
          y=1'b0;
          end
       else
          begin
          nst = cst;
          y=1'b0;
          end
S2: if (din == 1'b1)
          begin
         nst = S1;
          y=1'b1;
          end    
            else
          begin
          nst = S0;
          y=1'b1;
          end  
   default: nst = S0;
  endcase
end
always@(posedge clk)
begin
 if (reset)
   cst <= S0;
 else
   cst <= nst;
end
endmodul:-

Test Bench:-

module morfsm_tb;
reg din,clk,reset;
wire y;
morfsm m1(din, reset, clk, y);
initial
begin
reset=0       ;clk=0;din=0;
$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",din);
#10 din=1;
#10 din=1;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
//#5 reset=1;
//#5 reset=0;

end
always
#5 clk=~clk;
initial
#100 $finish ;
endmodule

Verilog Code:-

module melfsm(din, reset, clk, y);
output reg y;
input din;
input clk;
input reset;
reg [1:0] cst, nst;
parameter S0 = 2'b00,
          S1 = 2'b01,
          S2 = 2'b10,
always @(cst or din)
begin
case (cst)
   S0: if (din == 1'b1)
          begin
         nst = S1;
          y=1'b0;
          end
      else
          begin
          nst = cst;
          y=1'b0;
          end
S1: if (din == 1'b0)
          begin
        nst = S0;
          y=1'b1;
          end
       else
          begin
          nst = cst;
          y=1'b0;
          end
   default: nst = S0;
endcase
end
always@(posedge clk)
begin
if (reset)
   cst <= S0;
else
   cst <= nst;
end
endmodule

Test Bench:-

module melfsm_tb;
reg din,clk,reset;
wire y;
melfsm m1(din, reset, clk, y);
initial
begin
reset=0       ;clk=0;din=0;
$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",din);
#5 din=1;
#5 din=1;
#5 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#5 din=1;
//#5 reset=1;
//#5 reset=0;

end
always
#5 clk=~clk;
initial
#80 $finish ;
endmodule