Question

1. a) Given the two Verilog code segments, derive the schematics for the logic that will be synthesized from these blocks.

BLOCK 1

input Y;

reg A, B;

always @(posedge clk)

begin

A = Y;

B = A;

end

BLOCK 2

input Y;

reg A, B;

always @(posedge clk)

begin

A <= Y;

B <= A;

end

b) Define setup time by using timing diagrams. Explain what would happen if any one of these timing requirements are violated.

c) Describe worst delay path (slack) in digital systems design using schematics and timing diagrams. Explain its significance in terms of system performance.

Answer 1

Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly. In other words, each flip-flop (or any sequential element, in general) needs some time for the data to remain stable before the clock edge arrives, such that it can reliably capture the data. This duration is known as setup time.

The data that was launched at the previous clock edge should be stable at the input at least setup time before the clock edge. So, adherence to setup time ensures that the data launched at previous edge is captured properly at the current edge. In other words, we can also say that setup time adherence ensures that the system moves to next state smoothly.

Definition of Hold time: Hold time is defined as the minimum amount of time after the clock's active edge during which data must be stable. Similar to setup time, each sequential element needs some time for data to remain stable after clock edge arrives to reliably capture data. This duration is known as hold time.