Question

Verilog counter problem:

Using the attached 4-bit up-counter module and testbench as a template, write a Verilog module that implements a certain 4-bit counter. The module should include two more input variables: “updown” and “count2”.

If “updown” is 1, the circuit should count up (by 1s); if it is 0 it should count down (by 1s).

If “count2” has a value of 1, the circuit should instead count up by 2s; otherwise it will have no effect (the circuit counts normally up or down by 1s).

(Hint: use “if” and “else if” statements. After checking the “Resetn” value, check the value of “count2”).

Simulate the module in EDA Playground. In the testbench, use the following input signals:

    Clock = 0;                       // initial value

    updown = 1;                  // initially count up

    count2 = 0;                    // count-by-2 disabled

    Resetn = 0;                    // reset active

    En = 1;                                           // enable active

    #10

    Resetn = 1;                    // reset disabled

    #40

    updown = 0;                  // count down

    #80

    count2 = 1;                    // count-up-by-2 enabled

    #40

Answer 1

module counter_4_bit(updown,count2,count_value,Clock,Resetn,En);
input updown,count2,Clock,Resetn,En;
output reg[3:0] count_value;

always @(posedge Clock)
   begin
       if(Resetn == 1'b0)
           begin
               count_value <= 4'd0;
           end
       else if(En == 1'b0)
           begin
               count_value <= count_value;
           end
       else if(count2 == 1'b1)
           begin
               count_value <= count_value + 4'd2;
           end
       else if(updown == 1'b0)
           begin
               count_value <= count_value - 4'd1;
           end
       else if(updown == 1'b1)
           begin
               count_value <= count_value + 4'd1;
           end
       else
           begin
               count_value <= 4'dx;
           end
   end
endmodule

module test_bench(updown,count2,count_value,Clock,Resetn,En);
output reg updown,count2,Clock,Resetn,En;
input[3:0] count_value;

counter_4_bit counter(.updown(updown),.count2(count2),.count_value(count_value),.Clock(Clock),.Resetn(Resetn),.En(En));

initial
   begin
       updown = 1'b1;
       count2 = 1'b0;
       Resetn = 1'b0;
       En = 1'b1;
#10;
       Resetn = 1'b1;
#40;
       updown = 1'b0;
#80;
       count2 = 1'b1;
#40;
       $finish;
   end

initial
   begin
       Clock = 1'b0;
       forever
       begin
#2           Clock = ~Clock;
           $strobe($time,"\tcount = %d\n",counter.count_value);
          
       end
   end
initial
   begin
       $recordfile("haha.trn");
       $recordvars();
   end
endmodule

output is pasted below:

              Time       count value

                   2   count = 0

                   4   count = 0

                   6   count = 0

                   8   count = 0

                  10   count = 1

                  12   count = 1

                  14   count = 2

                  16   count = 2

                  18   count = 3

                  20   count = 3

                  22   count = 4

                  24   count = 4

                  26   count = 5

                  28   count = 5

                  30   count = 6

                  32   count = 6

                  34   count = 7

                  36   count = 7

                  38   count = 8

                  40   count = 8

                  42   count = 9

                  44   count = 9

                  46   count = 10

                  48   count = 10

                  50   count = 9

                  52   count = 9

                  54   count = 8

                  56   count = 8

                  58   count = 7

                  60   count = 7

                  62   count = 6

                  64   count = 6

                  66   count = 5

                  68   count = 5

                  70   count = 4

                  72   count = 4

                  74   count = 3

                  76   count = 3

                  78   count = 2

                  80   count = 2

                  82   count = 1

                  84   count = 1

                  86   count = 0

                  88   count = 0

                  90   count = 15

                  92   count = 15

                  94   count = 14

                  96   count = 14

                  98   count = 13

                 100   count = 13

                 102   count = 12

                 104   count = 12

                 106   count = 11

                 108   count = 11

                 110   count = 10

                 112   count = 10

                 114   count = 9

                 116   count = 9

                 118   count = 8

                 120   count = 8

                 122   count = 7

                 124   count = 7

                 126   count = 6

                 128   count = 6

                 130   count = 8

                 132   count = 8

                 134   count = 10

                 136   count = 10

                 138   count = 12

                 140   count = 12

                 142   count = 14

                 144   count = 14

                 146   count = 0

                 148   count = 0

                 150   count = 2

                 152   count = 2

                 154   count = 4

                 156   count = 4

                 158   count = 6

                 160   count = 6

                 162   count = 8

                 164   count = 8

                 166   count = 10

                 168   count = 10