Question

Question B

Write an 8 bit adder module in System Verilog by appropriately connecting two 4 bit adders (the System Verilog code of a 4 bit adder is available in the lecture notes). Instantiate your 8 bit adder module on DE2 board. Design a test circuit on DE2 board that allows us to test the 8 bit adder using the switches and the seven segment displays on DE2 board. The test circuit will need the module you designed for Part (a).

Im Using Quartus II to compile and run the Code , Im using a DE2 boards (Cyclone II EP2C35F672 FPGA with 35000 logic elements) . Could you please explain how i can compile and successfully run part B (above). Im new to using Quartus II

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My Code from Part A

Top Level Code

module hardware_level(SW, HEX0);

input wire [3:0] SW;

output wire [6:0] HEX0;

// create an instance of the project1_7seg module

// project1_7seg (A, B, C, D, S);

project1_7seg inst0( .A(SW[3]), .B(SW[2]), .C(SW[1]), .D(SW[0]), .S(HEX0));

endmodule

7 Segment Display Code

module project1_7seg( A, B, C, D, S);

input wire A, B, C, D;

output wire [6:0]S;

assign S[0] = ~A&~B&~C&D | ~A&B&~C&~D | A&B&~C&D | A&~B&C&D;

assign S[1] = ~A&B&~C&D | A&B&~D | A&C&D | B&C&~D;

assign S[2] = ~A&~B&C&~D | A&B&C;

assign S[3] = B&C&D | ~B&~C&D |~A&B&~C&~D | A&~B&C&~D;

assign S[4] = ~A&D | ~A&B&~C | ~B&~C&D;

assign S[5] = ~A&~B&D | ~A&~B&C | ~A&C&D | A&B&~C&D;

assign S[6] = ~A&~B&~C | ~A&B&C&D | A&B&~C&~D;

endmodule

Answer 1

       Create one top module which will instantiate both 8 bit adder and sevensegment display simultaneously and compile the program without any errors. Then dump the code into FPGA to get the output.
8 BIT ADDER:

module EightBitAdder(
input [7:0] a,
input [7:0] b,
//input cin,
output cout,  //carry; will be sent as OP, but won't be further used.
output [7:0] sout  //sum, sent as OP
);

wire try;

begin 
FullAdder mg0(.a_(a[0]), .b_(b[0]), .cin_(0), .cout_(try), .sout_(sout[0]));
FullAdder mg1(.a_(a[1]), .b_(b[1]), .cin_(try), .cout_(try), .sout_(sout[1]));
FullAdder mg2(.a_(a[2]), .b_(b[2]), .cin_(try), .cout_(try), .sout_(sout[2]));
FullAdder mg3(.a_(a[3]), .b_(b[3]), .cin_(try), .cout_(try), .sout_(sout[3]));
FullAdder mg4(.a_(a[4]), .b_(b[4]), .cin_(try), .cout_(try), .sout_(sout[4]));
FullAdder mg5(.a_(a[5]), .b_(b[5]), .cin_(try), .cout_(try), .sout_(sout[5]));
FullAdder mg6(.a_(a[6]), .b_(b[6]), .cin_(try), .cout_(try), .sout_(sout[6]));
FullAdder mg7(.a_(a[7]), .b_(b[7]), .cin_(try), .cout_(try), .sout_(sout[7]));
end
endmodule

FULL ADDER:
module FullAdder(
input a_,
input b_,
input cin_,
output sout_,
output cout_
);
wire temp1, temp2, temp3;

assign sout_ = a_ ^ b_ ^ cin_;
assign cout_ = ((a_ & b_) | (b_ & cin_) | (cin_ & a_));

endmodule