Question

Create a testbench in Verilog for the following module (logic). Verify the testbench works in your answer. I'll upvote correct answers.

This module does the following. The algorithm takes an input between 0 and 255 (in unsigned binary and counts the number of ones in each number (ex. 01010101 has 4 ones). Then the output would be 00000100 (4 in binary because there are 4 ones.

The test bench would need to verify the inputs and outputs of each number. Test 5 different numbers and ensure the output is expected for the input.

module logic(
  input [7:0] A, //input is between 0-255, so 8 bits.
  output reg [3:0] ones // 0-3 because, at max there can be 8 ones. As, 8 can be represented in 3 bits.
  );

integer i;// declaration of vailable i

always@(A)
begin
ones = 0;  //initialize count variable.
  for(i=0;i<8;i=i+1)   //Iterate all the bits. As input lies between 0 & 255, so, 8 bits.
ones = ones + A[i]; //Adding the bit to the count.
end

endmodule

Answer 1

code:

output :

raw_code :

`timescale 1ns / 1ps
module testlogic;

reg [7:0] A; //declaring input
wire [3:0]ones; //declaring outptu

logic v(.A(A),.ones(ones)); //instantiation of logic module

initial begin
$monitor("A = %b , ones = %d",A,ones); //to display output
end

initial
begin
#10 A = 8'b01010101; // checking with test cases
#100 A = 8'b00000100;
#200 A = 8'b00110001;
#400 A = 8'b00000000;
#500 A = 8'b11111111;
end
endmodule

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