Question

Verilog counter problem:

Using the attached 4-bit up-counter module and testbench as a template, write a Verilog module that implements a certain 4-bit counter. The module should include two more input variables: “updown” and “count2”.

If “updown” is 1, the circuit should count up (by 1s); if it is 0 it should count down (by 1s).

If “count2” has a value of 1, the circuit should instead count up by 2s; otherwise it will have no effect (the circuit counts normally up or down by 1s).

(Hint: use “if” and “else if” statements. After checking the “Resetn” value, check the value of “count2”).

Simulate the module in EDA Playground. In the testbench, use the following input signals:

    Clock = 0;                       // initial value

    updown = 1;                  // initially count up

    count2 = 0;                    // count-by-2 disabled

    Resetn = 0;                    // reset active

    En = 1;                                           // enable active

    #10

    Resetn = 1;                    // reset disabled

    #40

    updown = 0;                  // count down

    #80

    count2 = 1;                    // count-up-by-2 enabled

    #40

Submit a printout your module (do not have to show the testbench) as well as a screenshot of the simulation results (waveforms

Answer 1

module counter_updown (
  input Clock, Resetn, En,
  input updown, count2,
  output reg [3:0] count
);

always @ (posedge Clock)
  begin
   if (!Resetn) // Asynchronous active high reset
   count <= 4'b0;
   else if (En)
   begin
   if (updown) // Count up
   count <= count + count2 + 1'b1;
   else // Count down
   count <= count - count2 - 1'b1;
   end
  end

endmodule

////////////////////////// TESTBENCH FILE ////////////////////////
module counter_updown_tb;
reg Clock, Resetn, En;
reg updown, count2;
wire [3:0] count;

counter_updown m1 (.Clock(Clock), .Resetn(Resetn), .En(En), .updown(updown), .count2(count2), .count(count));

always
  #5 Clock = !Clock;

initial
  begin
   $recordfile("file1.trn");
   $recordvars();
  end

initial
  begin
   Clock = 1'b0;
   Resetn = 1'b0;
   updown = 1'b1;
   count2 = 1'b0;
   En = 1'b1;

   #10;
   Resetn = 1'b1;
   #40;
   updown = 1'b0;
   #80;
   count2 = 1'b1;
   #40;
   $finish;
  end
endmodule