In: Electrical Engineering
Design an 8-bit adder. Show Verilog code and testbench.
//verilog top level code for 8 bit adder using full adders as internal module instantiations
module adder_8bit ( A,B,Cin,S,Cout);
//input ports declarations
input [7:0] A,B;
input Cin;
//output port declarations
output [7:0] S; //sum output
output Cout ; //carry output
//internal signal declarations
wire [6:0] c ;
//instantiaion of full adders
fulladder F0 ( A[0] , B[0] , Cin , S[0] , c[0] );
fulladder F1 ( A[1] , B[1] , c[0] , S[1] , c[1] );
fulladder F2 ( A[2] , B[2] , c[1] , S[2] , c[2] );
fulladder F3 ( A[3] , B[3] , c[2] , S[3] , c[3] );
fulladder F4 ( A[4] , B[4] , c[3] , S[4] , c[4] );
fulladder F5 ( A[5] , B[5] , c[4] , S[5] , c[5] );
fulladder F6 ( A[6] , B[6] , c[5] , S[6] , c[6] );
fulladder F7 ( A[7] , B[7] , c[6] , S[7] , Cout );
endmodule
// verilog code full adder module
module fulladder (
//input ports declarations
input A,B,Cin,
//output port declartions
output S,Cout);
//sum logic
assign S = (A ^ B ^ Cin);
//carry logic
assign Cout = ( A & B ) | ( B & Cin) | (A & Cin) ;
endmodule
// verilog testbench code for top module of 8 bit adder
module test_adder_8bit ;
//inputs
reg [7:0] A,B;
reg Cin;
//outputs
wire [7:0] S;
wire Cout;
//instantiate UUT (unit under test) of top module
adder_8bit UUT (.A(A),.B(B),.Cin(Cin),.S(S),.Cout(Cout));
//input stimulus generations
initial begin
$dumpfile ("waves.vcd");
$dumpvars;
A = 8'b00101101 ; B = 8'b00101101; Cin = 1'b0; #10;
A = 8'b00100101 ; B = 8'b00100001; Cin = 1'b0; #10;
A = 8'b10100001 ; B = 8'b10101101; Cin = 1'b0; #10;
A = 8'b00100000 ; B = 8'b00100001; Cin = 1'b0; #10;
A = 8'b10101101 ; B = 8'b00101101; Cin = 1'b0; #10;
A = 8'b11101111 ; B = 8'b00100000; Cin = 1'b1; #10;
$finish;
end
endmodule
// Simulation waveforms